1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_FETCH_HH__
33#define __CPU_O3_FETCH_HH__
34
35#include "arch/utility.hh"
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38#include "cpu/pc_event.hh"
39#include "mem/packet_impl.hh"
40#include "mem/port.hh"
41#include "sim/eventq.hh"
42
43/**
44 * DefaultFetch class handles both single threaded and SMT fetch. Its
45 * width is specified by the parameters; each cycle it tries to fetch
46 * that many instructions. It supports using a branch predictor to
47 * predict direction and targets.
48 * It supports the idling functionality of the CPU by indicating to
49 * the CPU when it is active and inactive.
50 */
51template <class Impl>
52class DefaultFetch
53{
54 public:
55 /** Typedefs from Impl. */
56 typedef typename Impl::CPUPol CPUPol;
57 typedef typename Impl::DynInst DynInst;
58 typedef typename Impl::DynInstPtr DynInstPtr;
59 typedef typename Impl::O3CPU O3CPU;
60 typedef typename Impl::Params Params;
61
62 /** Typedefs from the CPU policy. */
63 typedef typename CPUPol::BPredUnit BPredUnit;
64 typedef typename CPUPol::FetchStruct FetchStruct;
65 typedef typename CPUPol::TimeStruct TimeStruct;
66
67 /** Typedefs from ISA. */
68 typedef TheISA::MachInst MachInst;
69 typedef TheISA::ExtMachInst ExtMachInst;
70
71 /** IcachePort class for DefaultFetch. Handles doing the
72 * communication with the cache/memory.
73 */
74 class IcachePort : public Port
75 {
76 protected:
77 /** Pointer to fetch. */
78 DefaultFetch<Impl> *fetch;
79
80 public:
81 /** Default constructor. */
82 IcachePort(DefaultFetch<Impl> *_fetch)
83 : Port(_fetch->name() + "-iport"), fetch(_fetch)
84 { }
85
86 protected:
87 /** Atomic version of receive. Panics. */
88 virtual Tick recvAtomic(PacketPtr pkt);
89
90 /** Functional version of receive. Panics. */
91 virtual void recvFunctional(PacketPtr pkt);
92
93 /** Receives status change. Other than range changing, panics. */
94 virtual void recvStatusChange(Status status);
95
96 /** Returns the address ranges of this device. */
97 virtual void getDeviceAddressRanges(AddrRangeList &resp,
98 AddrRangeList &snoop)
99 { resp.clear(); snoop.clear(); }
100
101 /** Timing version of receive. Handles setting fetch to the
102 * proper status to start fetching. */
103 virtual bool recvTiming(PacketPtr pkt);
104
105 /** Handles doing a retry of a failed fetch. */
106 virtual void recvRetry();
107 };
108
109 public:
110 /** Overall fetch status. Used to determine if the CPU can
111 * deschedule itsef due to a lack of activity.
112 */
113 enum FetchStatus {
114 Active,
115 Inactive
116 };
117
118 /** Individual thread status. */
119 enum ThreadStatus {
120 Running,
121 Idle,
122 Squashing,
123 Blocked,
124 Fetching,
125 TrapPending,
126 QuiescePending,
127 SwitchOut,
128 IcacheWaitResponse,
129 IcacheWaitRetry,
130 IcacheAccessComplete
131 };
132
133 /** Fetching Policy, Add new policies here.*/
134 enum FetchPriority {
135 SingleThread,
136 RoundRobin,
137 Branch,
138 IQ,
139 LSQ
140 };
141
142 private:
143 /** Fetch status. */
144 FetchStatus _status;
145
146 /** Per-thread status. */
147 ThreadStatus fetchStatus[Impl::MaxThreads];
148
149 /** Fetch policy. */
150 FetchPriority fetchPolicy;
151
152 /** List that has the threads organized by priority. */
153 std::list<unsigned> priorityList;
154
155 public:
156 /** DefaultFetch constructor. */
157 DefaultFetch(Params *params);
158
159 /** Returns the name of fetch. */
160 std::string name() const;
161
162 /** Registers statistics. */
163 void regStats();
164
165 /** Sets CPU pointer. */
166 void setCPU(O3CPU *cpu_ptr);
167
168 /** Sets the main backwards communication time buffer pointer. */
169 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
170
171 /** Sets pointer to list of active threads. */
172 void setActiveThreads(std::list<unsigned> *at_ptr);
173
174 /** Sets pointer to time buffer used to communicate to the next stage. */
175 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
176
177 /** Initialize stage. */
178 void initStage();
179
180 /** Processes cache completion event. */
181 void processCacheCompletion(PacketPtr pkt);
182
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_FETCH_HH__
33#define __CPU_O3_FETCH_HH__
34
35#include "arch/utility.hh"
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38#include "cpu/pc_event.hh"
39#include "mem/packet_impl.hh"
40#include "mem/port.hh"
41#include "sim/eventq.hh"
42
43/**
44 * DefaultFetch class handles both single threaded and SMT fetch. Its
45 * width is specified by the parameters; each cycle it tries to fetch
46 * that many instructions. It supports using a branch predictor to
47 * predict direction and targets.
48 * It supports the idling functionality of the CPU by indicating to
49 * the CPU when it is active and inactive.
50 */
51template <class Impl>
52class DefaultFetch
53{
54 public:
55 /** Typedefs from Impl. */
56 typedef typename Impl::CPUPol CPUPol;
57 typedef typename Impl::DynInst DynInst;
58 typedef typename Impl::DynInstPtr DynInstPtr;
59 typedef typename Impl::O3CPU O3CPU;
60 typedef typename Impl::Params Params;
61
62 /** Typedefs from the CPU policy. */
63 typedef typename CPUPol::BPredUnit BPredUnit;
64 typedef typename CPUPol::FetchStruct FetchStruct;
65 typedef typename CPUPol::TimeStruct TimeStruct;
66
67 /** Typedefs from ISA. */
68 typedef TheISA::MachInst MachInst;
69 typedef TheISA::ExtMachInst ExtMachInst;
70
71 /** IcachePort class for DefaultFetch. Handles doing the
72 * communication with the cache/memory.
73 */
74 class IcachePort : public Port
75 {
76 protected:
77 /** Pointer to fetch. */
78 DefaultFetch<Impl> *fetch;
79
80 public:
81 /** Default constructor. */
82 IcachePort(DefaultFetch<Impl> *_fetch)
83 : Port(_fetch->name() + "-iport"), fetch(_fetch)
84 { }
85
86 protected:
87 /** Atomic version of receive. Panics. */
88 virtual Tick recvAtomic(PacketPtr pkt);
89
90 /** Functional version of receive. Panics. */
91 virtual void recvFunctional(PacketPtr pkt);
92
93 /** Receives status change. Other than range changing, panics. */
94 virtual void recvStatusChange(Status status);
95
96 /** Returns the address ranges of this device. */
97 virtual void getDeviceAddressRanges(AddrRangeList &resp,
98 AddrRangeList &snoop)
99 { resp.clear(); snoop.clear(); }
100
101 /** Timing version of receive. Handles setting fetch to the
102 * proper status to start fetching. */
103 virtual bool recvTiming(PacketPtr pkt);
104
105 /** Handles doing a retry of a failed fetch. */
106 virtual void recvRetry();
107 };
108
109 public:
110 /** Overall fetch status. Used to determine if the CPU can
111 * deschedule itsef due to a lack of activity.
112 */
113 enum FetchStatus {
114 Active,
115 Inactive
116 };
117
118 /** Individual thread status. */
119 enum ThreadStatus {
120 Running,
121 Idle,
122 Squashing,
123 Blocked,
124 Fetching,
125 TrapPending,
126 QuiescePending,
127 SwitchOut,
128 IcacheWaitResponse,
129 IcacheWaitRetry,
130 IcacheAccessComplete
131 };
132
133 /** Fetching Policy, Add new policies here.*/
134 enum FetchPriority {
135 SingleThread,
136 RoundRobin,
137 Branch,
138 IQ,
139 LSQ
140 };
141
142 private:
143 /** Fetch status. */
144 FetchStatus _status;
145
146 /** Per-thread status. */
147 ThreadStatus fetchStatus[Impl::MaxThreads];
148
149 /** Fetch policy. */
150 FetchPriority fetchPolicy;
151
152 /** List that has the threads organized by priority. */
153 std::list<unsigned> priorityList;
154
155 public:
156 /** DefaultFetch constructor. */
157 DefaultFetch(Params *params);
158
159 /** Returns the name of fetch. */
160 std::string name() const;
161
162 /** Registers statistics. */
163 void regStats();
164
165 /** Sets CPU pointer. */
166 void setCPU(O3CPU *cpu_ptr);
167
168 /** Sets the main backwards communication time buffer pointer. */
169 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
170
171 /** Sets pointer to list of active threads. */
172 void setActiveThreads(std::list<unsigned> *at_ptr);
173
174 /** Sets pointer to time buffer used to communicate to the next stage. */
175 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
176
177 /** Initialize stage. */
178 void initStage();
179
180 /** Processes cache completion event. */
181 void processCacheCompletion(PacketPtr pkt);
182
|
189 /** Takes over from another CPU's thread. */
190 void takeOverFrom();
191
192 /** Checks if the fetch stage is switched out. */
193 bool isSwitchedOut() { return switchedOut; }
194
195 /** Tells fetch to wake up from a quiesce instruction. */
196 void wakeFromQuiesce();
197
198 private:
199 /** Changes the status of this stage to active, and indicates this
200 * to the CPU.
201 */
202 inline void switchToActive();
203
204 /** Changes the status of this stage to inactive, and indicates
205 * this to the CPU.
206 */
207 inline void switchToInactive();
208
209 /**
210 * Looks up in the branch predictor to see if the next PC should be
211 * either next PC+=MachInst or a branch target.
212 * @param next_PC Next PC variable passed in by reference. It is
213 * expected to be set to the current PC; it will be updated with what
214 * the next PC will be.
215 * @return Whether or not a branch was predicted as taken.
216 */
217 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC);
218
219 /**
220 * Fetches the cache line that contains fetch_PC. Returns any
221 * fault that happened. Puts the data into the class variable
222 * cacheData.
223 * @param fetch_PC The PC address that is being fetched from.
224 * @param ret_fault The fault reference that will be set to the result of
225 * the icache access.
226 * @param tid Thread id.
227 * @return Any fault that occured.
228 */
229 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
230
231 /** Squashes a specific thread and resets the PC. */
232 inline void doSquash(const Addr &new_PC, unsigned tid);
233
234 /** Squashes a specific thread and resets the PC. Also tells the CPU to
235 * remove any instructions between fetch and decode that should be sqaushed.
236 */
237 void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
238 unsigned tid);
239
240 /** Checks if a thread is stalled. */
241 bool checkStall(unsigned tid) const;
242
243 /** Updates overall fetch stage status; to be called at the end of each
244 * cycle. */
245 FetchStatus updateFetchStatus();
246
247 public:
248 /** Squashes a specific thread and resets the PC. Also tells the CPU to
249 * remove any instructions that are not in the ROB. The source of this
250 * squash should be the commit stage.
251 */
252 void squash(const Addr &new_PC, unsigned tid);
253
254 /** Ticks the fetch stage, processing all inputs signals and fetching
255 * as many instructions as possible.
256 */
257 void tick();
258
259 /** Checks all input signals and updates the status as necessary.
260 * @return: Returns if the status has changed due to input signals.
261 */
262 bool checkSignalsAndUpdate(unsigned tid);
263
264 /** Does the actual fetching of instructions and passing them on to the
265 * next stage.
266 * @param status_change fetch() sets this variable if there was a status
267 * change (ie switching to IcacheMissStall).
268 */
269 void fetch(bool &status_change);
270
271 /** Align a PC to the start of an I-cache block. */
272 Addr icacheBlockAlignPC(Addr addr)
273 {
274 addr = TheISA::realPCToFetchPC(addr);
275 return (addr & ~(cacheBlkMask));
276 }
277
278 private:
279 /** Handles retrying the fetch access. */
280 void recvRetry();
281
282 /** Returns the appropriate thread to fetch, given the fetch policy. */
283 int getFetchingThread(FetchPriority &fetch_priority);
284
285 /** Returns the appropriate thread to fetch using a round robin policy. */
286 int roundRobin();
287
288 /** Returns the appropriate thread to fetch using the IQ count policy. */
289 int iqCount();
290
291 /** Returns the appropriate thread to fetch using the LSQ count policy. */
292 int lsqCount();
293
294 /** Returns the appropriate thread to fetch using the branch count policy. */
295 int branchCount();
296
297 private:
298 /** Pointer to the O3CPU. */
299 O3CPU *cpu;
300
301 /** Time buffer interface. */
302 TimeBuffer<TimeStruct> *timeBuffer;
303
304 /** Wire to get decode's information from backwards time buffer. */
305 typename TimeBuffer<TimeStruct>::wire fromDecode;
306
307 /** Wire to get rename's information from backwards time buffer. */
308 typename TimeBuffer<TimeStruct>::wire fromRename;
309
310 /** Wire to get iew's information from backwards time buffer. */
311 typename TimeBuffer<TimeStruct>::wire fromIEW;
312
313 /** Wire to get commit's information from backwards time buffer. */
314 typename TimeBuffer<TimeStruct>::wire fromCommit;
315
316 /** Internal fetch instruction queue. */
317 TimeBuffer<FetchStruct> *fetchQueue;
318
319 //Might be annoying how this name is different than the queue.
320 /** Wire used to write any information heading to decode. */
321 typename TimeBuffer<FetchStruct>::wire toDecode;
322
323 MemObject *mem;
324
325 /** Icache interface. */
326 IcachePort *icachePort;
327
328 /** BPredUnit. */
329 BPredUnit branchPred;
330
331 /** Per-thread fetch PC. */
332 Addr PC[Impl::MaxThreads];
333
334 /** Per-thread next PC. */
335 Addr nextPC[Impl::MaxThreads];
336
337#if THE_ISA != ALPHA_ISA
338 /** Per-thread next Next PC.
339 * This is not a real register but is used for
340 * architectures that use a branch-delay slot.
341 * (such as MIPS or Sparc)
342 */
343 Addr nextNPC[Impl::MaxThreads];
344#endif
345
346 /** Memory request used to access cache. */
347 RequestPtr memReq[Impl::MaxThreads];
348
349 /** Variable that tracks if fetch has written to the time buffer this
350 * cycle. Used to tell CPU if there is activity this cycle.
351 */
352 bool wroteToTimeBuffer;
353
354 /** Tracks how many instructions has been fetched this cycle. */
355 int numInst;
356
357 /** Source of possible stalls. */
358 struct Stalls {
359 bool decode;
360 bool rename;
361 bool iew;
362 bool commit;
363 };
364
365 /** Tracks which stages are telling fetch to stall. */
366 Stalls stalls[Impl::MaxThreads];
367
368 /** Decode to fetch delay, in ticks. */
369 unsigned decodeToFetchDelay;
370
371 /** Rename to fetch delay, in ticks. */
372 unsigned renameToFetchDelay;
373
374 /** IEW to fetch delay, in ticks. */
375 unsigned iewToFetchDelay;
376
377 /** Commit to fetch delay, in ticks. */
378 unsigned commitToFetchDelay;
379
380 /** The width of fetch in instructions. */
381 unsigned fetchWidth;
382
383 /** Is the cache blocked? If so no threads can access it. */
384 bool cacheBlocked;
385
386 /** The packet that is waiting to be retried. */
387 PacketPtr retryPkt;
388
389 /** The thread that is waiting on the cache to tell fetch to retry. */
390 int retryTid;
391
392 /** Cache block size. */
393 int cacheBlkSize;
394
395 /** Mask to get a cache block's address. */
396 Addr cacheBlkMask;
397
398 /** The cache line being fetched. */
399 uint8_t *cacheData[Impl::MaxThreads];
400
401 /** Size of instructions. */
402 int instSize;
403
404 /** Icache stall statistics. */
405 Counter lastIcacheStall[Impl::MaxThreads];
406
407 /** List of Active Threads */
408 std::list<unsigned> *activeThreads;
409
410 /** Number of threads. */
411 unsigned numThreads;
412
413 /** Number of threads that are actively fetching. */
414 unsigned numFetchingThreads;
415
416 /** Thread ID being fetched. */
417 int threadFetched;
418
419 /** Checks if there is an interrupt pending. If there is, fetch
420 * must stop once it is not fetching PAL instructions.
421 */
422 bool interruptPending;
423
| 192 /** Takes over from another CPU's thread. */
193 void takeOverFrom();
194
195 /** Checks if the fetch stage is switched out. */
196 bool isSwitchedOut() { return switchedOut; }
197
198 /** Tells fetch to wake up from a quiesce instruction. */
199 void wakeFromQuiesce();
200
201 private:
202 /** Changes the status of this stage to active, and indicates this
203 * to the CPU.
204 */
205 inline void switchToActive();
206
207 /** Changes the status of this stage to inactive, and indicates
208 * this to the CPU.
209 */
210 inline void switchToInactive();
211
212 /**
213 * Looks up in the branch predictor to see if the next PC should be
214 * either next PC+=MachInst or a branch target.
215 * @param next_PC Next PC variable passed in by reference. It is
216 * expected to be set to the current PC; it will be updated with what
217 * the next PC will be.
218 * @return Whether or not a branch was predicted as taken.
219 */
220 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC);
221
222 /**
223 * Fetches the cache line that contains fetch_PC. Returns any
224 * fault that happened. Puts the data into the class variable
225 * cacheData.
226 * @param fetch_PC The PC address that is being fetched from.
227 * @param ret_fault The fault reference that will be set to the result of
228 * the icache access.
229 * @param tid Thread id.
230 * @return Any fault that occured.
231 */
232 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
233
234 /** Squashes a specific thread and resets the PC. */
235 inline void doSquash(const Addr &new_PC, unsigned tid);
236
237 /** Squashes a specific thread and resets the PC. Also tells the CPU to
238 * remove any instructions between fetch and decode that should be sqaushed.
239 */
240 void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
241 unsigned tid);
242
243 /** Checks if a thread is stalled. */
244 bool checkStall(unsigned tid) const;
245
246 /** Updates overall fetch stage status; to be called at the end of each
247 * cycle. */
248 FetchStatus updateFetchStatus();
249
250 public:
251 /** Squashes a specific thread and resets the PC. Also tells the CPU to
252 * remove any instructions that are not in the ROB. The source of this
253 * squash should be the commit stage.
254 */
255 void squash(const Addr &new_PC, unsigned tid);
256
257 /** Ticks the fetch stage, processing all inputs signals and fetching
258 * as many instructions as possible.
259 */
260 void tick();
261
262 /** Checks all input signals and updates the status as necessary.
263 * @return: Returns if the status has changed due to input signals.
264 */
265 bool checkSignalsAndUpdate(unsigned tid);
266
267 /** Does the actual fetching of instructions and passing them on to the
268 * next stage.
269 * @param status_change fetch() sets this variable if there was a status
270 * change (ie switching to IcacheMissStall).
271 */
272 void fetch(bool &status_change);
273
274 /** Align a PC to the start of an I-cache block. */
275 Addr icacheBlockAlignPC(Addr addr)
276 {
277 addr = TheISA::realPCToFetchPC(addr);
278 return (addr & ~(cacheBlkMask));
279 }
280
281 private:
282 /** Handles retrying the fetch access. */
283 void recvRetry();
284
285 /** Returns the appropriate thread to fetch, given the fetch policy. */
286 int getFetchingThread(FetchPriority &fetch_priority);
287
288 /** Returns the appropriate thread to fetch using a round robin policy. */
289 int roundRobin();
290
291 /** Returns the appropriate thread to fetch using the IQ count policy. */
292 int iqCount();
293
294 /** Returns the appropriate thread to fetch using the LSQ count policy. */
295 int lsqCount();
296
297 /** Returns the appropriate thread to fetch using the branch count policy. */
298 int branchCount();
299
300 private:
301 /** Pointer to the O3CPU. */
302 O3CPU *cpu;
303
304 /** Time buffer interface. */
305 TimeBuffer<TimeStruct> *timeBuffer;
306
307 /** Wire to get decode's information from backwards time buffer. */
308 typename TimeBuffer<TimeStruct>::wire fromDecode;
309
310 /** Wire to get rename's information from backwards time buffer. */
311 typename TimeBuffer<TimeStruct>::wire fromRename;
312
313 /** Wire to get iew's information from backwards time buffer. */
314 typename TimeBuffer<TimeStruct>::wire fromIEW;
315
316 /** Wire to get commit's information from backwards time buffer. */
317 typename TimeBuffer<TimeStruct>::wire fromCommit;
318
319 /** Internal fetch instruction queue. */
320 TimeBuffer<FetchStruct> *fetchQueue;
321
322 //Might be annoying how this name is different than the queue.
323 /** Wire used to write any information heading to decode. */
324 typename TimeBuffer<FetchStruct>::wire toDecode;
325
326 MemObject *mem;
327
328 /** Icache interface. */
329 IcachePort *icachePort;
330
331 /** BPredUnit. */
332 BPredUnit branchPred;
333
334 /** Per-thread fetch PC. */
335 Addr PC[Impl::MaxThreads];
336
337 /** Per-thread next PC. */
338 Addr nextPC[Impl::MaxThreads];
339
340#if THE_ISA != ALPHA_ISA
341 /** Per-thread next Next PC.
342 * This is not a real register but is used for
343 * architectures that use a branch-delay slot.
344 * (such as MIPS or Sparc)
345 */
346 Addr nextNPC[Impl::MaxThreads];
347#endif
348
349 /** Memory request used to access cache. */
350 RequestPtr memReq[Impl::MaxThreads];
351
352 /** Variable that tracks if fetch has written to the time buffer this
353 * cycle. Used to tell CPU if there is activity this cycle.
354 */
355 bool wroteToTimeBuffer;
356
357 /** Tracks how many instructions has been fetched this cycle. */
358 int numInst;
359
360 /** Source of possible stalls. */
361 struct Stalls {
362 bool decode;
363 bool rename;
364 bool iew;
365 bool commit;
366 };
367
368 /** Tracks which stages are telling fetch to stall. */
369 Stalls stalls[Impl::MaxThreads];
370
371 /** Decode to fetch delay, in ticks. */
372 unsigned decodeToFetchDelay;
373
374 /** Rename to fetch delay, in ticks. */
375 unsigned renameToFetchDelay;
376
377 /** IEW to fetch delay, in ticks. */
378 unsigned iewToFetchDelay;
379
380 /** Commit to fetch delay, in ticks. */
381 unsigned commitToFetchDelay;
382
383 /** The width of fetch in instructions. */
384 unsigned fetchWidth;
385
386 /** Is the cache blocked? If so no threads can access it. */
387 bool cacheBlocked;
388
389 /** The packet that is waiting to be retried. */
390 PacketPtr retryPkt;
391
392 /** The thread that is waiting on the cache to tell fetch to retry. */
393 int retryTid;
394
395 /** Cache block size. */
396 int cacheBlkSize;
397
398 /** Mask to get a cache block's address. */
399 Addr cacheBlkMask;
400
401 /** The cache line being fetched. */
402 uint8_t *cacheData[Impl::MaxThreads];
403
404 /** Size of instructions. */
405 int instSize;
406
407 /** Icache stall statistics. */
408 Counter lastIcacheStall[Impl::MaxThreads];
409
410 /** List of Active Threads */
411 std::list<unsigned> *activeThreads;
412
413 /** Number of threads. */
414 unsigned numThreads;
415
416 /** Number of threads that are actively fetching. */
417 unsigned numFetchingThreads;
418
419 /** Thread ID being fetched. */
420 int threadFetched;
421
422 /** Checks if there is an interrupt pending. If there is, fetch
423 * must stop once it is not fetching PAL instructions.
424 */
425 bool interruptPending;
426
|