1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_FETCH_HH__
32#define __CPU_O3_FETCH_HH__
33
34#include "arch/utility.hh"
35#include "base/statistics.hh"
36#include "base/timebuf.hh"
37#include "cpu/pc_event.hh"
38#include "mem/packet.hh"
39#include "mem/port.hh"
40#include "sim/eventq.hh"
41
42class Sampler;
43
44/**
45 * DefaultFetch class handles both single threaded and SMT fetch. Its
46 * width is specified by the parameters; each cycle it tries to fetch
47 * that many instructions. It supports using a branch predictor to
48 * predict direction and targets.
49 * It supports the idling functionality of the CPU by indicating to
50 * the CPU when it is active and inactive.
51 */
52template <class Impl>
53class DefaultFetch
54{
55 public:
56 /** Typedefs from Impl. */
57 typedef typename Impl::CPUPol CPUPol;
58 typedef typename Impl::DynInst DynInst;
59 typedef typename Impl::DynInstPtr DynInstPtr;
60 typedef typename Impl::FullCPU FullCPU;
61 typedef typename Impl::Params Params;
62
63 /** Typedefs from the CPU policy. */
64 typedef typename CPUPol::BPredUnit BPredUnit;
65 typedef typename CPUPol::FetchStruct FetchStruct;
66 typedef typename CPUPol::TimeStruct TimeStruct;
67
68 /** Typedefs from ISA. */
69 typedef TheISA::MachInst MachInst;
70 typedef TheISA::ExtMachInst ExtMachInst;
71
72 /** IcachePort class for DefaultFetch. Handles doing the
73 * communication with the cache/memory.
74 */
75 class IcachePort : public Port
76 {
77 protected:
78 /** Pointer to fetch. */
79 DefaultFetch<Impl> *fetch;
80
81 public:
82 /** Default constructor. */
83 IcachePort(DefaultFetch<Impl> *_fetch)
84 : Port(_fetch->name() + "-iport"), fetch(_fetch)
85 { }
86
87 protected:
88 /** Atomic version of receive. Panics. */
89 virtual Tick recvAtomic(PacketPtr pkt);
90
91 /** Functional version of receive. Panics. */
92 virtual void recvFunctional(PacketPtr pkt);
93
94 /** Receives status change. Other than range changing, panics. */
95 virtual void recvStatusChange(Status status);
96
97 /** Returns the address ranges of this device. */
98 virtual void getDeviceAddressRanges(AddrRangeList &resp,
99 AddrRangeList &snoop)
100 { resp.clear(); snoop.clear(); }
101
102 /** Timing version of receive. Handles setting fetch to the
103 * proper status to start fetching. */
104 virtual bool recvTiming(PacketPtr pkt);
105
106 /** Handles doing a retry of a failed fetch. */
107 virtual void recvRetry();
108 };
109
110 public:
111 /** Overall fetch status. Used to determine if the CPU can
112 * deschedule itsef due to a lack of activity.
113 */
114 enum FetchStatus {
115 Active,
116 Inactive
117 };
118
119 /** Individual thread status. */
120 enum ThreadStatus {
121 Running,
122 Idle,
123 Squashing,
124 Blocked,
125 Fetching,
126 TrapPending,
127 QuiescePending,
128 SwitchOut,
129 IcacheWaitResponse,
130 IcacheWaitRetry,
131 IcacheAccessComplete
132 };
133
134 /** Fetching Policy, Add new policies here.*/
135 enum FetchPriority {
136 SingleThread,
137 RoundRobin,
138 Branch,
139 IQ,
140 LSQ
141 };
142
143 private:
144 /** Fetch status. */
145 FetchStatus _status;
146
147 /** Per-thread status. */
148 ThreadStatus fetchStatus[Impl::MaxThreads];
149
150 /** Fetch policy. */
151 FetchPriority fetchPolicy;
152
153 /** List that has the threads organized by priority. */
154 std::list<unsigned> priorityList;
155
156 public:
157 /** DefaultFetch constructor. */
158 DefaultFetch(Params *params);
159
160 /** Returns the name of fetch. */
161 std::string name() const;
162
163 /** Registers statistics. */
164 void regStats();
165
166 /** Sets CPU pointer. */
167 void setCPU(FullCPU *cpu_ptr);
168
169 /** Sets the main backwards communication time buffer pointer. */
170 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
171
172 /** Sets pointer to list of active threads. */
173 void setActiveThreads(std::list<unsigned> *at_ptr);
174
175 /** Sets pointer to time buffer used to communicate to the next stage. */
176 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
177
178 /** Initialize stage. */
179 void initStage();
180
181 /** Processes cache completion event. */
182 void processCacheCompletion(PacketPtr pkt);
183
184 /** Begins the switch out of the fetch stage. */
185 void switchOut();
186
187 /** Completes the switch out of the fetch stage. */
188 void doSwitchOut();
189
190 /** Takes over from another CPU's thread. */
191 void takeOverFrom();
192
193 /** Checks if the fetch stage is switched out. */
194 bool isSwitchedOut() { return switchedOut; }
195
196 /** Tells fetch to wake up from a quiesce instruction. */
197 void wakeFromQuiesce();
198
199 private:
200 /** Changes the status of this stage to active, and indicates this
201 * to the CPU.
202 */
203 inline void switchToActive();
204
205 /** Changes the status of this stage to inactive, and indicates
206 * this to the CPU.
207 */
208 inline void switchToInactive();
209
210 /**
211 * Looks up in the branch predictor to see if the next PC should be
212 * either next PC+=MachInst or a branch target.
213 * @param next_PC Next PC variable passed in by reference. It is
214 * expected to be set to the current PC; it will be updated with what
215 * the next PC will be.
216 * @return Whether or not a branch was predicted as taken.
217 */
218 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC);
219
220 /**
221 * Fetches the cache line that contains fetch_PC. Returns any
222 * fault that happened. Puts the data into the class variable
223 * cacheData.
224 * @param fetch_PC The PC address that is being fetched from.
225 * @param ret_fault The fault reference that will be set to the result of
226 * the icache access.
227 * @param tid Thread id.
228 * @return Any fault that occured.
229 */
230 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
231
232 /** Squashes a specific thread and resets the PC. */
233 inline void doSquash(const Addr &new_PC, unsigned tid);
234
235 /** Squashes a specific thread and resets the PC. Also tells the CPU to
236 * remove any instructions between fetch and decode that should be sqaushed.
237 */
238 void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
239 unsigned tid);
240
241 /** Checks if a thread is stalled. */
242 bool checkStall(unsigned tid) const;
243
244 /** Updates overall fetch stage status; to be called at the end of each
245 * cycle. */
246 FetchStatus updateFetchStatus();
247
248 public:
249 /** Squashes a specific thread and resets the PC. Also tells the CPU to
250 * remove any instructions that are not in the ROB. The source of this
251 * squash should be the commit stage.
252 */
253 void squash(const Addr &new_PC, unsigned tid);
254
255 /** Ticks the fetch stage, processing all inputs signals and fetching
256 * as many instructions as possible.
257 */
258 void tick();
259
260 /** Checks all input signals and updates the status as necessary.
261 * @return: Returns if the status has changed due to input signals.
262 */
263 bool checkSignalsAndUpdate(unsigned tid);
264
265 /** Does the actual fetching of instructions and passing them on to the
266 * next stage.
267 * @param status_change fetch() sets this variable if there was a status
268 * change (ie switching to IcacheMissStall).
269 */
270 void fetch(bool &status_change);
271
272 /** Align a PC to the start of an I-cache block. */
273 Addr icacheBlockAlignPC(Addr addr)
274 {
275 addr = TheISA::realPCToFetchPC(addr);
276 return (addr & ~(cacheBlkMask));
277 }
278
279 private:
280 /** Handles retrying the fetch access. */
281 void recvRetry();
282
283 /** Returns the appropriate thread to fetch, given the fetch policy. */
284 int getFetchingThread(FetchPriority &fetch_priority);
285
286 /** Returns the appropriate thread to fetch using a round robin policy. */
287 int roundRobin();
288
289 /** Returns the appropriate thread to fetch using the IQ count policy. */
290 int iqCount();
291
292 /** Returns the appropriate thread to fetch using the LSQ count policy. */
293 int lsqCount();
294
295 /** Returns the appropriate thread to fetch using the branch count policy. */
296 int branchCount();
297
298 private:
299 /** Pointer to the FullCPU. */
300 FullCPU *cpu;
301
302 /** Time buffer interface. */
303 TimeBuffer<TimeStruct> *timeBuffer;
304
305 /** Wire to get decode's information from backwards time buffer. */
306 typename TimeBuffer<TimeStruct>::wire fromDecode;
307
308 /** Wire to get rename's information from backwards time buffer. */
309 typename TimeBuffer<TimeStruct>::wire fromRename;
310
311 /** Wire to get iew's information from backwards time buffer. */
312 typename TimeBuffer<TimeStruct>::wire fromIEW;
313
314 /** Wire to get commit's information from backwards time buffer. */
315 typename TimeBuffer<TimeStruct>::wire fromCommit;
316
317 /** Internal fetch instruction queue. */
318 TimeBuffer<FetchStruct> *fetchQueue;
319
320 //Might be annoying how this name is different than the queue.
321 /** Wire used to write any information heading to decode. */
322 typename TimeBuffer<FetchStruct>::wire toDecode;
323
324 MemObject *mem;
325
326 /** Icache interface. */
327 IcachePort *icachePort;
328
329 /** BPredUnit. */
330 BPredUnit branchPred;
331
332 /** Per-thread fetch PC. */
333 Addr PC[Impl::MaxThreads];
334
335 /** Per-thread next PC. */
336 Addr nextPC[Impl::MaxThreads];
337
338 /** Memory request used to access cache. */
339 RequestPtr memReq[Impl::MaxThreads];
340
341 /** Variable that tracks if fetch has written to the time buffer this
342 * cycle. Used to tell CPU if there is activity this cycle.
343 */
344 bool wroteToTimeBuffer;
345
346 /** Tracks how many instructions has been fetched this cycle. */
347 int numInst;
348
349 /** Source of possible stalls. */
350 struct Stalls {
351 bool decode;
352 bool rename;
353 bool iew;
354 bool commit;
355 };
356
357 /** Tracks which stages are telling fetch to stall. */
358 Stalls stalls[Impl::MaxThreads];
359
360 /** Decode to fetch delay, in ticks. */
361 unsigned decodeToFetchDelay;
362
363 /** Rename to fetch delay, in ticks. */
364 unsigned renameToFetchDelay;
365
366 /** IEW to fetch delay, in ticks. */
367 unsigned iewToFetchDelay;
368
369 /** Commit to fetch delay, in ticks. */
370 unsigned commitToFetchDelay;
371
372 /** The width of fetch in instructions. */
373 unsigned fetchWidth;
374
375 /** Is the cache blocked? If so no threads can access it. */
376 bool cacheBlocked;
377
378 /** The packet that is waiting to be retried. */
379 PacketPtr retryPkt;
380
381 /** The thread that is waiting on the cache to tell fetch to retry. */
382 int retryTid;
383
384 /** Cache block size. */
385 int cacheBlkSize;
386
387 /** Mask to get a cache block's address. */
388 Addr cacheBlkMask;
389
390 /** The cache line being fetched. */
391 uint8_t *cacheData[Impl::MaxThreads];
392
393 /** Size of instructions. */
394 int instSize;
395
396 /** Icache stall statistics. */
397 Counter lastIcacheStall[Impl::MaxThreads];
398
399 /** List of Active Threads */
400 std::list<unsigned> *activeThreads;
401
402 /** Number of threads. */
403 unsigned numThreads;
404
405 /** Number of threads that are actively fetching. */
406 unsigned numFetchingThreads;
407
408 /** Thread ID being fetched. */
409 int threadFetched;
410
411 /** Checks if there is an interrupt pending. If there is, fetch
412 * must stop once it is not fetching PAL instructions.
413 */
414 bool interruptPending;
415
416 /** Records if fetch is switched out. */
417 bool switchedOut;
418
419 // @todo: Consider making these vectors and tracking on a per thread basis.
420 /** Stat for total number of cycles stalled due to an icache miss. */
421 Stats::Scalar<> icacheStallCycles;
422 /** Stat for total number of fetched instructions. */
423 Stats::Scalar<> fetchedInsts;
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_FETCH_HH__
32#define __CPU_O3_FETCH_HH__
33
34#include "arch/utility.hh"
35#include "base/statistics.hh"
36#include "base/timebuf.hh"
37#include "cpu/pc_event.hh"
38#include "mem/packet.hh"
39#include "mem/port.hh"
40#include "sim/eventq.hh"
41
42class Sampler;
43
44/**
45 * DefaultFetch class handles both single threaded and SMT fetch. Its
46 * width is specified by the parameters; each cycle it tries to fetch
47 * that many instructions. It supports using a branch predictor to
48 * predict direction and targets.
49 * It supports the idling functionality of the CPU by indicating to
50 * the CPU when it is active and inactive.
51 */
52template <class Impl>
53class DefaultFetch
54{
55 public:
56 /** Typedefs from Impl. */
57 typedef typename Impl::CPUPol CPUPol;
58 typedef typename Impl::DynInst DynInst;
59 typedef typename Impl::DynInstPtr DynInstPtr;
60 typedef typename Impl::FullCPU FullCPU;
61 typedef typename Impl::Params Params;
62
63 /** Typedefs from the CPU policy. */
64 typedef typename CPUPol::BPredUnit BPredUnit;
65 typedef typename CPUPol::FetchStruct FetchStruct;
66 typedef typename CPUPol::TimeStruct TimeStruct;
67
68 /** Typedefs from ISA. */
69 typedef TheISA::MachInst MachInst;
70 typedef TheISA::ExtMachInst ExtMachInst;
71
72 /** IcachePort class for DefaultFetch. Handles doing the
73 * communication with the cache/memory.
74 */
75 class IcachePort : public Port
76 {
77 protected:
78 /** Pointer to fetch. */
79 DefaultFetch<Impl> *fetch;
80
81 public:
82 /** Default constructor. */
83 IcachePort(DefaultFetch<Impl> *_fetch)
84 : Port(_fetch->name() + "-iport"), fetch(_fetch)
85 { }
86
87 protected:
88 /** Atomic version of receive. Panics. */
89 virtual Tick recvAtomic(PacketPtr pkt);
90
91 /** Functional version of receive. Panics. */
92 virtual void recvFunctional(PacketPtr pkt);
93
94 /** Receives status change. Other than range changing, panics. */
95 virtual void recvStatusChange(Status status);
96
97 /** Returns the address ranges of this device. */
98 virtual void getDeviceAddressRanges(AddrRangeList &resp,
99 AddrRangeList &snoop)
100 { resp.clear(); snoop.clear(); }
101
102 /** Timing version of receive. Handles setting fetch to the
103 * proper status to start fetching. */
104 virtual bool recvTiming(PacketPtr pkt);
105
106 /** Handles doing a retry of a failed fetch. */
107 virtual void recvRetry();
108 };
109
110 public:
111 /** Overall fetch status. Used to determine if the CPU can
112 * deschedule itsef due to a lack of activity.
113 */
114 enum FetchStatus {
115 Active,
116 Inactive
117 };
118
119 /** Individual thread status. */
120 enum ThreadStatus {
121 Running,
122 Idle,
123 Squashing,
124 Blocked,
125 Fetching,
126 TrapPending,
127 QuiescePending,
128 SwitchOut,
129 IcacheWaitResponse,
130 IcacheWaitRetry,
131 IcacheAccessComplete
132 };
133
134 /** Fetching Policy, Add new policies here.*/
135 enum FetchPriority {
136 SingleThread,
137 RoundRobin,
138 Branch,
139 IQ,
140 LSQ
141 };
142
143 private:
144 /** Fetch status. */
145 FetchStatus _status;
146
147 /** Per-thread status. */
148 ThreadStatus fetchStatus[Impl::MaxThreads];
149
150 /** Fetch policy. */
151 FetchPriority fetchPolicy;
152
153 /** List that has the threads organized by priority. */
154 std::list<unsigned> priorityList;
155
156 public:
157 /** DefaultFetch constructor. */
158 DefaultFetch(Params *params);
159
160 /** Returns the name of fetch. */
161 std::string name() const;
162
163 /** Registers statistics. */
164 void regStats();
165
166 /** Sets CPU pointer. */
167 void setCPU(FullCPU *cpu_ptr);
168
169 /** Sets the main backwards communication time buffer pointer. */
170 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
171
172 /** Sets pointer to list of active threads. */
173 void setActiveThreads(std::list<unsigned> *at_ptr);
174
175 /** Sets pointer to time buffer used to communicate to the next stage. */
176 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
177
178 /** Initialize stage. */
179 void initStage();
180
181 /** Processes cache completion event. */
182 void processCacheCompletion(PacketPtr pkt);
183
184 /** Begins the switch out of the fetch stage. */
185 void switchOut();
186
187 /** Completes the switch out of the fetch stage. */
188 void doSwitchOut();
189
190 /** Takes over from another CPU's thread. */
191 void takeOverFrom();
192
193 /** Checks if the fetch stage is switched out. */
194 bool isSwitchedOut() { return switchedOut; }
195
196 /** Tells fetch to wake up from a quiesce instruction. */
197 void wakeFromQuiesce();
198
199 private:
200 /** Changes the status of this stage to active, and indicates this
201 * to the CPU.
202 */
203 inline void switchToActive();
204
205 /** Changes the status of this stage to inactive, and indicates
206 * this to the CPU.
207 */
208 inline void switchToInactive();
209
210 /**
211 * Looks up in the branch predictor to see if the next PC should be
212 * either next PC+=MachInst or a branch target.
213 * @param next_PC Next PC variable passed in by reference. It is
214 * expected to be set to the current PC; it will be updated with what
215 * the next PC will be.
216 * @return Whether or not a branch was predicted as taken.
217 */
218 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC);
219
220 /**
221 * Fetches the cache line that contains fetch_PC. Returns any
222 * fault that happened. Puts the data into the class variable
223 * cacheData.
224 * @param fetch_PC The PC address that is being fetched from.
225 * @param ret_fault The fault reference that will be set to the result of
226 * the icache access.
227 * @param tid Thread id.
228 * @return Any fault that occured.
229 */
230 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
231
232 /** Squashes a specific thread and resets the PC. */
233 inline void doSquash(const Addr &new_PC, unsigned tid);
234
235 /** Squashes a specific thread and resets the PC. Also tells the CPU to
236 * remove any instructions between fetch and decode that should be sqaushed.
237 */
238 void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
239 unsigned tid);
240
241 /** Checks if a thread is stalled. */
242 bool checkStall(unsigned tid) const;
243
244 /** Updates overall fetch stage status; to be called at the end of each
245 * cycle. */
246 FetchStatus updateFetchStatus();
247
248 public:
249 /** Squashes a specific thread and resets the PC. Also tells the CPU to
250 * remove any instructions that are not in the ROB. The source of this
251 * squash should be the commit stage.
252 */
253 void squash(const Addr &new_PC, unsigned tid);
254
255 /** Ticks the fetch stage, processing all inputs signals and fetching
256 * as many instructions as possible.
257 */
258 void tick();
259
260 /** Checks all input signals and updates the status as necessary.
261 * @return: Returns if the status has changed due to input signals.
262 */
263 bool checkSignalsAndUpdate(unsigned tid);
264
265 /** Does the actual fetching of instructions and passing them on to the
266 * next stage.
267 * @param status_change fetch() sets this variable if there was a status
268 * change (ie switching to IcacheMissStall).
269 */
270 void fetch(bool &status_change);
271
272 /** Align a PC to the start of an I-cache block. */
273 Addr icacheBlockAlignPC(Addr addr)
274 {
275 addr = TheISA::realPCToFetchPC(addr);
276 return (addr & ~(cacheBlkMask));
277 }
278
279 private:
280 /** Handles retrying the fetch access. */
281 void recvRetry();
282
283 /** Returns the appropriate thread to fetch, given the fetch policy. */
284 int getFetchingThread(FetchPriority &fetch_priority);
285
286 /** Returns the appropriate thread to fetch using a round robin policy. */
287 int roundRobin();
288
289 /** Returns the appropriate thread to fetch using the IQ count policy. */
290 int iqCount();
291
292 /** Returns the appropriate thread to fetch using the LSQ count policy. */
293 int lsqCount();
294
295 /** Returns the appropriate thread to fetch using the branch count policy. */
296 int branchCount();
297
298 private:
299 /** Pointer to the FullCPU. */
300 FullCPU *cpu;
301
302 /** Time buffer interface. */
303 TimeBuffer<TimeStruct> *timeBuffer;
304
305 /** Wire to get decode's information from backwards time buffer. */
306 typename TimeBuffer<TimeStruct>::wire fromDecode;
307
308 /** Wire to get rename's information from backwards time buffer. */
309 typename TimeBuffer<TimeStruct>::wire fromRename;
310
311 /** Wire to get iew's information from backwards time buffer. */
312 typename TimeBuffer<TimeStruct>::wire fromIEW;
313
314 /** Wire to get commit's information from backwards time buffer. */
315 typename TimeBuffer<TimeStruct>::wire fromCommit;
316
317 /** Internal fetch instruction queue. */
318 TimeBuffer<FetchStruct> *fetchQueue;
319
320 //Might be annoying how this name is different than the queue.
321 /** Wire used to write any information heading to decode. */
322 typename TimeBuffer<FetchStruct>::wire toDecode;
323
324 MemObject *mem;
325
326 /** Icache interface. */
327 IcachePort *icachePort;
328
329 /** BPredUnit. */
330 BPredUnit branchPred;
331
332 /** Per-thread fetch PC. */
333 Addr PC[Impl::MaxThreads];
334
335 /** Per-thread next PC. */
336 Addr nextPC[Impl::MaxThreads];
337
338 /** Memory request used to access cache. */
339 RequestPtr memReq[Impl::MaxThreads];
340
341 /** Variable that tracks if fetch has written to the time buffer this
342 * cycle. Used to tell CPU if there is activity this cycle.
343 */
344 bool wroteToTimeBuffer;
345
346 /** Tracks how many instructions has been fetched this cycle. */
347 int numInst;
348
349 /** Source of possible stalls. */
350 struct Stalls {
351 bool decode;
352 bool rename;
353 bool iew;
354 bool commit;
355 };
356
357 /** Tracks which stages are telling fetch to stall. */
358 Stalls stalls[Impl::MaxThreads];
359
360 /** Decode to fetch delay, in ticks. */
361 unsigned decodeToFetchDelay;
362
363 /** Rename to fetch delay, in ticks. */
364 unsigned renameToFetchDelay;
365
366 /** IEW to fetch delay, in ticks. */
367 unsigned iewToFetchDelay;
368
369 /** Commit to fetch delay, in ticks. */
370 unsigned commitToFetchDelay;
371
372 /** The width of fetch in instructions. */
373 unsigned fetchWidth;
374
375 /** Is the cache blocked? If so no threads can access it. */
376 bool cacheBlocked;
377
378 /** The packet that is waiting to be retried. */
379 PacketPtr retryPkt;
380
381 /** The thread that is waiting on the cache to tell fetch to retry. */
382 int retryTid;
383
384 /** Cache block size. */
385 int cacheBlkSize;
386
387 /** Mask to get a cache block's address. */
388 Addr cacheBlkMask;
389
390 /** The cache line being fetched. */
391 uint8_t *cacheData[Impl::MaxThreads];
392
393 /** Size of instructions. */
394 int instSize;
395
396 /** Icache stall statistics. */
397 Counter lastIcacheStall[Impl::MaxThreads];
398
399 /** List of Active Threads */
400 std::list<unsigned> *activeThreads;
401
402 /** Number of threads. */
403 unsigned numThreads;
404
405 /** Number of threads that are actively fetching. */
406 unsigned numFetchingThreads;
407
408 /** Thread ID being fetched. */
409 int threadFetched;
410
411 /** Checks if there is an interrupt pending. If there is, fetch
412 * must stop once it is not fetching PAL instructions.
413 */
414 bool interruptPending;
415
416 /** Records if fetch is switched out. */
417 bool switchedOut;
418
419 // @todo: Consider making these vectors and tracking on a per thread basis.
420 /** Stat for total number of cycles stalled due to an icache miss. */
421 Stats::Scalar<> icacheStallCycles;
422 /** Stat for total number of fetched instructions. */
423 Stats::Scalar<> fetchedInsts;
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