1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_FETCH_HH__
32#define __CPU_O3_FETCH_HH__
33
34#include "arch/utility.hh"
35#include "base/statistics.hh"
36#include "base/timebuf.hh"
37#include "cpu/pc_event.hh"
38#include "mem/packet.hh"
39#include "mem/port.hh"
40#include "sim/eventq.hh"
41
42class Sampler;
43
44/**
45 * DefaultFetch class handles both single threaded and SMT fetch. Its
46 * width is specified by the parameters; each cycle it tries to fetch
47 * that many instructions. It supports using a branch predictor to
48 * predict direction and targets.
49 * It supports the idling functionality of the CPU by indicating to
50 * the CPU when it is active and inactive.
51 */
52template <class Impl>
53class DefaultFetch
54{
55 public:
56 /** Typedefs from Impl. */
57 typedef typename Impl::CPUPol CPUPol;
58 typedef typename Impl::DynInst DynInst;
59 typedef typename Impl::DynInstPtr DynInstPtr;
60 typedef typename Impl::FullCPU FullCPU;
61 typedef typename Impl::Params Params;
62
63 /** Typedefs from the CPU policy. */
64 typedef typename CPUPol::BPredUnit BPredUnit;
65 typedef typename CPUPol::FetchStruct FetchStruct;
66 typedef typename CPUPol::TimeStruct TimeStruct;
67
68 /** Typedefs from ISA. */
69 typedef TheISA::MachInst MachInst;
70 typedef TheISA::ExtMachInst ExtMachInst;
71
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_FETCH_HH__
32#define __CPU_O3_FETCH_HH__
33
34#include "arch/utility.hh"
35#include "base/statistics.hh"
36#include "base/timebuf.hh"
37#include "cpu/pc_event.hh"
38#include "mem/packet.hh"
39#include "mem/port.hh"
40#include "sim/eventq.hh"
41
42class Sampler;
43
44/**
45 * DefaultFetch class handles both single threaded and SMT fetch. Its
46 * width is specified by the parameters; each cycle it tries to fetch
47 * that many instructions. It supports using a branch predictor to
48 * predict direction and targets.
49 * It supports the idling functionality of the CPU by indicating to
50 * the CPU when it is active and inactive.
51 */
52template <class Impl>
53class DefaultFetch
54{
55 public:
56 /** Typedefs from Impl. */
57 typedef typename Impl::CPUPol CPUPol;
58 typedef typename Impl::DynInst DynInst;
59 typedef typename Impl::DynInstPtr DynInstPtr;
60 typedef typename Impl::FullCPU FullCPU;
61 typedef typename Impl::Params Params;
62
63 /** Typedefs from the CPU policy. */
64 typedef typename CPUPol::BPredUnit BPredUnit;
65 typedef typename CPUPol::FetchStruct FetchStruct;
66 typedef typename CPUPol::TimeStruct TimeStruct;
67
68 /** Typedefs from ISA. */
69 typedef TheISA::MachInst MachInst;
70 typedef TheISA::ExtMachInst ExtMachInst;
71
|
| 72 /** IcachePort class for DefaultFetch. Handles doing the
73 * communication with the cache/memory.
74 */
|
72 class IcachePort : public Port
73 {
74 protected:
| 75 class IcachePort : public Port
76 {
77 protected:
|
| 78 /** Pointer to fetch. */
|
75 DefaultFetch<Impl> *fetch;
76
77 public:
| 79 DefaultFetch<Impl> *fetch;
80
81 public:
|
| 82 /** Default constructor. */
|
78 IcachePort(DefaultFetch<Impl> *_fetch)
79 : Port(_fetch->name() + "-iport"), fetch(_fetch)
80 { }
81
82 protected:
| 83 IcachePort(DefaultFetch<Impl> *_fetch)
84 : Port(_fetch->name() + "-iport"), fetch(_fetch)
85 { }
86
87 protected:
|
| 88 /** Atomic version of receive. Panics. */
|
83 virtual Tick recvAtomic(PacketPtr pkt);
84
| 89 virtual Tick recvAtomic(PacketPtr pkt);
90
|
| 91 /** Functional version of receive. Panics. */
|
85 virtual void recvFunctional(PacketPtr pkt);
86
| 92 virtual void recvFunctional(PacketPtr pkt);
93
|
| 94 /** Receives status change. Other than range changing, panics. */
|
87 virtual void recvStatusChange(Status status);
88
| 95 virtual void recvStatusChange(Status status);
96
|
| 97 /** Returns the address ranges of this device. */
|
89 virtual void getDeviceAddressRanges(AddrRangeList &resp,
90 AddrRangeList &snoop)
91 { resp.clear(); snoop.clear(); }
92
| 98 virtual void getDeviceAddressRanges(AddrRangeList &resp,
99 AddrRangeList &snoop)
100 { resp.clear(); snoop.clear(); }
101
|
| 102 /** Timing version of receive. Handles setting fetch to the
103 * proper status to start fetching. */
|
93 virtual bool recvTiming(PacketPtr pkt);
94
| 104 virtual bool recvTiming(PacketPtr pkt);
105
|
| 106 /** Handles doing a retry of a failed fetch. */
|
95 virtual void recvRetry();
96 };
97
98 public:
99 /** Overall fetch status. Used to determine if the CPU can
100 * deschedule itsef due to a lack of activity.
101 */
102 enum FetchStatus {
103 Active,
104 Inactive
105 };
106
107 /** Individual thread status. */
108 enum ThreadStatus {
109 Running,
110 Idle,
111 Squashing,
112 Blocked,
113 Fetching,
114 TrapPending,
115 QuiescePending,
116 SwitchOut,
117 IcacheWaitResponse,
118 IcacheWaitRetry,
119 IcacheAccessComplete
120 };
121
122 /** Fetching Policy, Add new policies here.*/
123 enum FetchPriority {
124 SingleThread,
125 RoundRobin,
126 Branch,
127 IQ,
128 LSQ
129 };
130
131 private:
132 /** Fetch status. */
133 FetchStatus _status;
134
135 /** Per-thread status. */
136 ThreadStatus fetchStatus[Impl::MaxThreads];
137
138 /** Fetch policy. */
139 FetchPriority fetchPolicy;
140
141 /** List that has the threads organized by priority. */
142 std::list<unsigned> priorityList;
143
144 public:
145 /** DefaultFetch constructor. */
146 DefaultFetch(Params *params);
147
148 /** Returns the name of fetch. */
149 std::string name() const;
150
151 /** Registers statistics. */
152 void regStats();
153
154 /** Sets CPU pointer. */
155 void setCPU(FullCPU *cpu_ptr);
156
157 /** Sets the main backwards communication time buffer pointer. */
158 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
159
160 /** Sets pointer to list of active threads. */
161 void setActiveThreads(std::list<unsigned> *at_ptr);
162
163 /** Sets pointer to time buffer used to communicate to the next stage. */
164 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
165
| 107 virtual void recvRetry();
108 };
109
110 public:
111 /** Overall fetch status. Used to determine if the CPU can
112 * deschedule itsef due to a lack of activity.
113 */
114 enum FetchStatus {
115 Active,
116 Inactive
117 };
118
119 /** Individual thread status. */
120 enum ThreadStatus {
121 Running,
122 Idle,
123 Squashing,
124 Blocked,
125 Fetching,
126 TrapPending,
127 QuiescePending,
128 SwitchOut,
129 IcacheWaitResponse,
130 IcacheWaitRetry,
131 IcacheAccessComplete
132 };
133
134 /** Fetching Policy, Add new policies here.*/
135 enum FetchPriority {
136 SingleThread,
137 RoundRobin,
138 Branch,
139 IQ,
140 LSQ
141 };
142
143 private:
144 /** Fetch status. */
145 FetchStatus _status;
146
147 /** Per-thread status. */
148 ThreadStatus fetchStatus[Impl::MaxThreads];
149
150 /** Fetch policy. */
151 FetchPriority fetchPolicy;
152
153 /** List that has the threads organized by priority. */
154 std::list<unsigned> priorityList;
155
156 public:
157 /** DefaultFetch constructor. */
158 DefaultFetch(Params *params);
159
160 /** Returns the name of fetch. */
161 std::string name() const;
162
163 /** Registers statistics. */
164 void regStats();
165
166 /** Sets CPU pointer. */
167 void setCPU(FullCPU *cpu_ptr);
168
169 /** Sets the main backwards communication time buffer pointer. */
170 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
171
172 /** Sets pointer to list of active threads. */
173 void setActiveThreads(std::list<unsigned> *at_ptr);
174
175 /** Sets pointer to time buffer used to communicate to the next stage. */
176 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
177
|
166 /** Sets pointer to page table. */
167// void setPageTable(PageTable *pt_ptr);
168
| |
169 /** Initialize stage. */
170 void initStage();
171
172 /** Processes cache completion event. */
173 void processCacheCompletion(PacketPtr pkt);
174
175 /** Begins the switch out of the fetch stage. */
176 void switchOut();
177
178 /** Completes the switch out of the fetch stage. */
179 void doSwitchOut();
180
181 /** Takes over from another CPU's thread. */
182 void takeOverFrom();
183
184 /** Checks if the fetch stage is switched out. */
185 bool isSwitchedOut() { return switchedOut; }
186
187 /** Tells fetch to wake up from a quiesce instruction. */
188 void wakeFromQuiesce();
189
190 private:
191 /** Changes the status of this stage to active, and indicates this
192 * to the CPU.
193 */
194 inline void switchToActive();
195
196 /** Changes the status of this stage to inactive, and indicates
197 * this to the CPU.
198 */
199 inline void switchToInactive();
200
201 /**
202 * Looks up in the branch predictor to see if the next PC should be
203 * either next PC+=MachInst or a branch target.
204 * @param next_PC Next PC variable passed in by reference. It is
205 * expected to be set to the current PC; it will be updated with what
206 * the next PC will be.
207 * @return Whether or not a branch was predicted as taken.
208 */
209 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC);
210
211 /**
212 * Fetches the cache line that contains fetch_PC. Returns any
213 * fault that happened. Puts the data into the class variable
214 * cacheData.
215 * @param fetch_PC The PC address that is being fetched from.
216 * @param ret_fault The fault reference that will be set to the result of
217 * the icache access.
218 * @param tid Thread id.
219 * @return Any fault that occured.
220 */
221 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
222
223 /** Squashes a specific thread and resets the PC. */
224 inline void doSquash(const Addr &new_PC, unsigned tid);
225
226 /** Squashes a specific thread and resets the PC. Also tells the CPU to
227 * remove any instructions between fetch and decode that should be sqaushed.
228 */
229 void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
230 unsigned tid);
231
232 /** Checks if a thread is stalled. */
233 bool checkStall(unsigned tid) const;
234
235 /** Updates overall fetch stage status; to be called at the end of each
236 * cycle. */
237 FetchStatus updateFetchStatus();
238
239 public:
240 /** Squashes a specific thread and resets the PC. Also tells the CPU to
241 * remove any instructions that are not in the ROB. The source of this
242 * squash should be the commit stage.
243 */
244 void squash(const Addr &new_PC, unsigned tid);
245
246 /** Ticks the fetch stage, processing all inputs signals and fetching
247 * as many instructions as possible.
248 */
249 void tick();
250
251 /** Checks all input signals and updates the status as necessary.
252 * @return: Returns if the status has changed due to input signals.
253 */
254 bool checkSignalsAndUpdate(unsigned tid);
255
256 /** Does the actual fetching of instructions and passing them on to the
257 * next stage.
258 * @param status_change fetch() sets this variable if there was a status
259 * change (ie switching to IcacheMissStall).
260 */
261 void fetch(bool &status_change);
262
263 /** Align a PC to the start of an I-cache block. */
264 Addr icacheBlockAlignPC(Addr addr)
265 {
266 addr = TheISA::realPCToFetchPC(addr);
267 return (addr & ~(cacheBlkMask));
268 }
269
270 private:
| 178 /** Initialize stage. */
179 void initStage();
180
181 /** Processes cache completion event. */
182 void processCacheCompletion(PacketPtr pkt);
183
184 /** Begins the switch out of the fetch stage. */
185 void switchOut();
186
187 /** Completes the switch out of the fetch stage. */
188 void doSwitchOut();
189
190 /** Takes over from another CPU's thread. */
191 void takeOverFrom();
192
193 /** Checks if the fetch stage is switched out. */
194 bool isSwitchedOut() { return switchedOut; }
195
196 /** Tells fetch to wake up from a quiesce instruction. */
197 void wakeFromQuiesce();
198
199 private:
200 /** Changes the status of this stage to active, and indicates this
201 * to the CPU.
202 */
203 inline void switchToActive();
204
205 /** Changes the status of this stage to inactive, and indicates
206 * this to the CPU.
207 */
208 inline void switchToInactive();
209
210 /**
211 * Looks up in the branch predictor to see if the next PC should be
212 * either next PC+=MachInst or a branch target.
213 * @param next_PC Next PC variable passed in by reference. It is
214 * expected to be set to the current PC; it will be updated with what
215 * the next PC will be.
216 * @return Whether or not a branch was predicted as taken.
217 */
218 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC);
219
220 /**
221 * Fetches the cache line that contains fetch_PC. Returns any
222 * fault that happened. Puts the data into the class variable
223 * cacheData.
224 * @param fetch_PC The PC address that is being fetched from.
225 * @param ret_fault The fault reference that will be set to the result of
226 * the icache access.
227 * @param tid Thread id.
228 * @return Any fault that occured.
229 */
230 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
231
232 /** Squashes a specific thread and resets the PC. */
233 inline void doSquash(const Addr &new_PC, unsigned tid);
234
235 /** Squashes a specific thread and resets the PC. Also tells the CPU to
236 * remove any instructions between fetch and decode that should be sqaushed.
237 */
238 void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
239 unsigned tid);
240
241 /** Checks if a thread is stalled. */
242 bool checkStall(unsigned tid) const;
243
244 /** Updates overall fetch stage status; to be called at the end of each
245 * cycle. */
246 FetchStatus updateFetchStatus();
247
248 public:
249 /** Squashes a specific thread and resets the PC. Also tells the CPU to
250 * remove any instructions that are not in the ROB. The source of this
251 * squash should be the commit stage.
252 */
253 void squash(const Addr &new_PC, unsigned tid);
254
255 /** Ticks the fetch stage, processing all inputs signals and fetching
256 * as many instructions as possible.
257 */
258 void tick();
259
260 /** Checks all input signals and updates the status as necessary.
261 * @return: Returns if the status has changed due to input signals.
262 */
263 bool checkSignalsAndUpdate(unsigned tid);
264
265 /** Does the actual fetching of instructions and passing them on to the
266 * next stage.
267 * @param status_change fetch() sets this variable if there was a status
268 * change (ie switching to IcacheMissStall).
269 */
270 void fetch(bool &status_change);
271
272 /** Align a PC to the start of an I-cache block. */
273 Addr icacheBlockAlignPC(Addr addr)
274 {
275 addr = TheISA::realPCToFetchPC(addr);
276 return (addr & ~(cacheBlkMask));
277 }
278
279 private:
|
| 280 /** Handles retrying the fetch access. */
|
271 void recvRetry();
272
273 /** Returns the appropriate thread to fetch, given the fetch policy. */
274 int getFetchingThread(FetchPriority &fetch_priority);
275
276 /** Returns the appropriate thread to fetch using a round robin policy. */
277 int roundRobin();
278
279 /** Returns the appropriate thread to fetch using the IQ count policy. */
280 int iqCount();
281
282 /** Returns the appropriate thread to fetch using the LSQ count policy. */
283 int lsqCount();
284
285 /** Returns the appropriate thread to fetch using the branch count policy. */
286 int branchCount();
287
288 private:
289 /** Pointer to the FullCPU. */
290 FullCPU *cpu;
291
292 /** Time buffer interface. */
293 TimeBuffer<TimeStruct> *timeBuffer;
294
295 /** Wire to get decode's information from backwards time buffer. */
296 typename TimeBuffer<TimeStruct>::wire fromDecode;
297
298 /** Wire to get rename's information from backwards time buffer. */
299 typename TimeBuffer<TimeStruct>::wire fromRename;
300
301 /** Wire to get iew's information from backwards time buffer. */
302 typename TimeBuffer<TimeStruct>::wire fromIEW;
303
304 /** Wire to get commit's information from backwards time buffer. */
305 typename TimeBuffer<TimeStruct>::wire fromCommit;
306
307 /** Internal fetch instruction queue. */
308 TimeBuffer<FetchStruct> *fetchQueue;
309
310 //Might be annoying how this name is different than the queue.
311 /** Wire used to write any information heading to decode. */
312 typename TimeBuffer<FetchStruct>::wire toDecode;
313
314 MemObject *mem;
315
316 /** Icache interface. */
317 IcachePort *icachePort;
318
319 /** BPredUnit. */
320 BPredUnit branchPred;
321
322 /** Per-thread fetch PC. */
323 Addr PC[Impl::MaxThreads];
324
325 /** Per-thread next PC. */
326 Addr nextPC[Impl::MaxThreads];
327
328 /** Memory request used to access cache. */
329 RequestPtr memReq[Impl::MaxThreads];
330
331 /** Variable that tracks if fetch has written to the time buffer this
332 * cycle. Used to tell CPU if there is activity this cycle.
333 */
334 bool wroteToTimeBuffer;
335
336 /** Tracks how many instructions has been fetched this cycle. */
337 int numInst;
338
339 /** Source of possible stalls. */
340 struct Stalls {
341 bool decode;
342 bool rename;
343 bool iew;
344 bool commit;
345 };
346
347 /** Tracks which stages are telling fetch to stall. */
348 Stalls stalls[Impl::MaxThreads];
349
350 /** Decode to fetch delay, in ticks. */
351 unsigned decodeToFetchDelay;
352
353 /** Rename to fetch delay, in ticks. */
354 unsigned renameToFetchDelay;
355
356 /** IEW to fetch delay, in ticks. */
357 unsigned iewToFetchDelay;
358
359 /** Commit to fetch delay, in ticks. */
360 unsigned commitToFetchDelay;
361
362 /** The width of fetch in instructions. */
363 unsigned fetchWidth;
364
365 /** Is the cache blocked? If so no threads can access it. */
366 bool cacheBlocked;
367
368 /** The packet that is waiting to be retried. */
369 PacketPtr retryPkt;
370
371 /** The thread that is waiting on the cache to tell fetch to retry. */
372 int retryTid;
373
374 /** Cache block size. */
375 int cacheBlkSize;
376
377 /** Mask to get a cache block's address. */
378 Addr cacheBlkMask;
379
380 /** The cache line being fetched. */
381 uint8_t *cacheData[Impl::MaxThreads];
382
383 /** Size of instructions. */
384 int instSize;
385
386 /** Icache stall statistics. */
387 Counter lastIcacheStall[Impl::MaxThreads];
388
389 /** List of Active Threads */
390 std::list<unsigned> *activeThreads;
391
392 /** Number of threads. */
393 unsigned numThreads;
394
395 /** Number of threads that are actively fetching. */
396 unsigned numFetchingThreads;
397
398 /** Thread ID being fetched. */
399 int threadFetched;
400
401 /** Checks if there is an interrupt pending. If there is, fetch
402 * must stop once it is not fetching PAL instructions.
403 */
404 bool interruptPending;
405
406 /** Records if fetch is switched out. */
407 bool switchedOut;
408
| 281 void recvRetry();
282
283 /** Returns the appropriate thread to fetch, given the fetch policy. */
284 int getFetchingThread(FetchPriority &fetch_priority);
285
286 /** Returns the appropriate thread to fetch using a round robin policy. */
287 int roundRobin();
288
289 /** Returns the appropriate thread to fetch using the IQ count policy. */
290 int iqCount();
291
292 /** Returns the appropriate thread to fetch using the LSQ count policy. */
293 int lsqCount();
294
295 /** Returns the appropriate thread to fetch using the branch count policy. */
296 int branchCount();
297
298 private:
299 /** Pointer to the FullCPU. */
300 FullCPU *cpu;
301
302 /** Time buffer interface. */
303 TimeBuffer<TimeStruct> *timeBuffer;
304
305 /** Wire to get decode's information from backwards time buffer. */
306 typename TimeBuffer<TimeStruct>::wire fromDecode;
307
308 /** Wire to get rename's information from backwards time buffer. */
309 typename TimeBuffer<TimeStruct>::wire fromRename;
310
311 /** Wire to get iew's information from backwards time buffer. */
312 typename TimeBuffer<TimeStruct>::wire fromIEW;
313
314 /** Wire to get commit's information from backwards time buffer. */
315 typename TimeBuffer<TimeStruct>::wire fromCommit;
316
317 /** Internal fetch instruction queue. */
318 TimeBuffer<FetchStruct> *fetchQueue;
319
320 //Might be annoying how this name is different than the queue.
321 /** Wire used to write any information heading to decode. */
322 typename TimeBuffer<FetchStruct>::wire toDecode;
323
324 MemObject *mem;
325
326 /** Icache interface. */
327 IcachePort *icachePort;
328
329 /** BPredUnit. */
330 BPredUnit branchPred;
331
332 /** Per-thread fetch PC. */
333 Addr PC[Impl::MaxThreads];
334
335 /** Per-thread next PC. */
336 Addr nextPC[Impl::MaxThreads];
337
338 /** Memory request used to access cache. */
339 RequestPtr memReq[Impl::MaxThreads];
340
341 /** Variable that tracks if fetch has written to the time buffer this
342 * cycle. Used to tell CPU if there is activity this cycle.
343 */
344 bool wroteToTimeBuffer;
345
346 /** Tracks how many instructions has been fetched this cycle. */
347 int numInst;
348
349 /** Source of possible stalls. */
350 struct Stalls {
351 bool decode;
352 bool rename;
353 bool iew;
354 bool commit;
355 };
356
357 /** Tracks which stages are telling fetch to stall. */
358 Stalls stalls[Impl::MaxThreads];
359
360 /** Decode to fetch delay, in ticks. */
361 unsigned decodeToFetchDelay;
362
363 /** Rename to fetch delay, in ticks. */
364 unsigned renameToFetchDelay;
365
366 /** IEW to fetch delay, in ticks. */
367 unsigned iewToFetchDelay;
368
369 /** Commit to fetch delay, in ticks. */
370 unsigned commitToFetchDelay;
371
372 /** The width of fetch in instructions. */
373 unsigned fetchWidth;
374
375 /** Is the cache blocked? If so no threads can access it. */
376 bool cacheBlocked;
377
378 /** The packet that is waiting to be retried. */
379 PacketPtr retryPkt;
380
381 /** The thread that is waiting on the cache to tell fetch to retry. */
382 int retryTid;
383
384 /** Cache block size. */
385 int cacheBlkSize;
386
387 /** Mask to get a cache block's address. */
388 Addr cacheBlkMask;
389
390 /** The cache line being fetched. */
391 uint8_t *cacheData[Impl::MaxThreads];
392
393 /** Size of instructions. */
394 int instSize;
395
396 /** Icache stall statistics. */
397 Counter lastIcacheStall[Impl::MaxThreads];
398
399 /** List of Active Threads */
400 std::list<unsigned> *activeThreads;
401
402 /** Number of threads. */
403 unsigned numThreads;
404
405 /** Number of threads that are actively fetching. */
406 unsigned numFetchingThreads;
407
408 /** Thread ID being fetched. */
409 int threadFetched;
410
411 /** Checks if there is an interrupt pending. If there is, fetch
412 * must stop once it is not fetching PAL instructions.
413 */
414 bool interruptPending;
415
416 /** Records if fetch is switched out. */
417 bool switchedOut;
418
|
409#if !FULL_SYSTEM
410 /** Page table pointer. */
411// PageTable *pTable;
412#endif
413
| |
414 // @todo: Consider making these vectors and tracking on a per thread basis.
415 /** Stat for total number of cycles stalled due to an icache miss. */
416 Stats::Scalar<> icacheStallCycles;
417 /** Stat for total number of fetched instructions. */
418 Stats::Scalar<> fetchedInsts;
419 Stats::Scalar<> fetchedBranches;
420 /** Stat for total number of predicted branches. */
421 Stats::Scalar<> predictedBranches;
422 /** Stat for total number of cycles spent fetching. */
423 Stats::Scalar<> fetchCycles;
424 /** Stat for total number of cycles spent squashing. */
425 Stats::Scalar<> fetchSquashCycles;
426 /** Stat for total number of cycles spent blocked due to other stages in
427 * the pipeline.
428 */
429 Stats::Scalar<> fetchIdleCycles;
430 /** Total number of cycles spent blocked. */
431 Stats::Scalar<> fetchBlockedCycles;
432 /** Total number of cycles spent in any other state. */
433 Stats::Scalar<> fetchMiscStallCycles;
434 /** Stat for total number of fetched cache lines. */
435 Stats::Scalar<> fetchedCacheLines;
436 /** Total number of outstanding icache accesses that were dropped
437 * due to a squash.
438 */
439 Stats::Scalar<> fetchIcacheSquashes;
440 /** Distribution of number of instructions fetched each cycle. */
441 Stats::Distribution<> fetchNisnDist;
442 /** Rate of how often fetch was idle. */
443 Stats::Formula idleRate;
444 /** Number of branch fetches per cycle. */
445 Stats::Formula branchRate;
446 /** Number of instruction fetched per cycle. */
447 Stats::Formula fetchRate;
448};
449
450#endif //__CPU_O3_FETCH_HH__
| 419 // @todo: Consider making these vectors and tracking on a per thread basis.
420 /** Stat for total number of cycles stalled due to an icache miss. */
421 Stats::Scalar<> icacheStallCycles;
422 /** Stat for total number of fetched instructions. */
423 Stats::Scalar<> fetchedInsts;
424 Stats::Scalar<> fetchedBranches;
425 /** Stat for total number of predicted branches. */
426 Stats::Scalar<> predictedBranches;
427 /** Stat for total number of cycles spent fetching. */
428 Stats::Scalar<> fetchCycles;
429 /** Stat for total number of cycles spent squashing. */
430 Stats::Scalar<> fetchSquashCycles;
431 /** Stat for total number of cycles spent blocked due to other stages in
432 * the pipeline.
433 */
434 Stats::Scalar<> fetchIdleCycles;
435 /** Total number of cycles spent blocked. */
436 Stats::Scalar<> fetchBlockedCycles;
437 /** Total number of cycles spent in any other state. */
438 Stats::Scalar<> fetchMiscStallCycles;
439 /** Stat for total number of fetched cache lines. */
440 Stats::Scalar<> fetchedCacheLines;
441 /** Total number of outstanding icache accesses that were dropped
442 * due to a squash.
443 */
444 Stats::Scalar<> fetchIcacheSquashes;
445 /** Distribution of number of instructions fetched each cycle. */
446 Stats::Distribution<> fetchNisnDist;
447 /** Rate of how often fetch was idle. */
448 Stats::Formula idleRate;
449 /** Number of branch fetches per cycle. */
450 Stats::Formula branchRate;
451 /** Number of instruction fetched per cycle. */
452 Stats::Formula fetchRate;
453};
454
455#endif //__CPU_O3_FETCH_HH__
|