fetch.hh (2696:30b38e36ff54) | fetch.hh (2698:d5f35d41e017) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 55 unchanged lines hidden (view full) --- 64 typedef typename CPUPol::BPredUnit BPredUnit; 65 typedef typename CPUPol::FetchStruct FetchStruct; 66 typedef typename CPUPol::TimeStruct TimeStruct; 67 68 /** Typedefs from ISA. */ 69 typedef TheISA::MachInst MachInst; 70 typedef TheISA::ExtMachInst ExtMachInst; 71 | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 55 unchanged lines hidden (view full) --- 64 typedef typename CPUPol::BPredUnit BPredUnit; 65 typedef typename CPUPol::FetchStruct FetchStruct; 66 typedef typename CPUPol::TimeStruct TimeStruct; 67 68 /** Typedefs from ISA. */ 69 typedef TheISA::MachInst MachInst; 70 typedef TheISA::ExtMachInst ExtMachInst; 71 |
72 /** IcachePort class for DefaultFetch. Handles doing the 73 * communication with the cache/memory. 74 */ |
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72 class IcachePort : public Port 73 { 74 protected: | 75 class IcachePort : public Port 76 { 77 protected: |
78 /** Pointer to fetch. */ |
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75 DefaultFetch<Impl> *fetch; 76 77 public: | 79 DefaultFetch<Impl> *fetch; 80 81 public: |
82 /** Default constructor. */ |
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78 IcachePort(DefaultFetch<Impl> *_fetch) 79 : Port(_fetch->name() + "-iport"), fetch(_fetch) 80 { } 81 82 protected: | 83 IcachePort(DefaultFetch<Impl> *_fetch) 84 : Port(_fetch->name() + "-iport"), fetch(_fetch) 85 { } 86 87 protected: |
88 /** Atomic version of receive. Panics. */ |
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83 virtual Tick recvAtomic(PacketPtr pkt); 84 | 89 virtual Tick recvAtomic(PacketPtr pkt); 90 |
91 /** Functional version of receive. Panics. */ |
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85 virtual void recvFunctional(PacketPtr pkt); 86 | 92 virtual void recvFunctional(PacketPtr pkt); 93 |
94 /** Receives status change. Other than range changing, panics. */ |
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87 virtual void recvStatusChange(Status status); 88 | 95 virtual void recvStatusChange(Status status); 96 |
97 /** Returns the address ranges of this device. */ |
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89 virtual void getDeviceAddressRanges(AddrRangeList &resp, 90 AddrRangeList &snoop) 91 { resp.clear(); snoop.clear(); } 92 | 98 virtual void getDeviceAddressRanges(AddrRangeList &resp, 99 AddrRangeList &snoop) 100 { resp.clear(); snoop.clear(); } 101 |
102 /** Timing version of receive. Handles setting fetch to the 103 * proper status to start fetching. */ |
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93 virtual bool recvTiming(PacketPtr pkt); 94 | 104 virtual bool recvTiming(PacketPtr pkt); 105 |
106 /** Handles doing a retry of a failed fetch. */ |
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95 virtual void recvRetry(); 96 }; 97 98 public: 99 /** Overall fetch status. Used to determine if the CPU can 100 * deschedule itsef due to a lack of activity. 101 */ 102 enum FetchStatus { --- 55 unchanged lines hidden (view full) --- 158 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 159 160 /** Sets pointer to list of active threads. */ 161 void setActiveThreads(std::list<unsigned> *at_ptr); 162 163 /** Sets pointer to time buffer used to communicate to the next stage. */ 164 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 165 | 107 virtual void recvRetry(); 108 }; 109 110 public: 111 /** Overall fetch status. Used to determine if the CPU can 112 * deschedule itsef due to a lack of activity. 113 */ 114 enum FetchStatus { --- 55 unchanged lines hidden (view full) --- 170 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 171 172 /** Sets pointer to list of active threads. */ 173 void setActiveThreads(std::list<unsigned> *at_ptr); 174 175 /** Sets pointer to time buffer used to communicate to the next stage. */ 176 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 177 |
166 /** Sets pointer to page table. */ 167// void setPageTable(PageTable *pt_ptr); 168 | |
169 /** Initialize stage. */ 170 void initStage(); 171 172 /** Processes cache completion event. */ 173 void processCacheCompletion(PacketPtr pkt); 174 175 /** Begins the switch out of the fetch stage. */ 176 void switchOut(); --- 86 unchanged lines hidden (view full) --- 263 /** Align a PC to the start of an I-cache block. */ 264 Addr icacheBlockAlignPC(Addr addr) 265 { 266 addr = TheISA::realPCToFetchPC(addr); 267 return (addr & ~(cacheBlkMask)); 268 } 269 270 private: | 178 /** Initialize stage. */ 179 void initStage(); 180 181 /** Processes cache completion event. */ 182 void processCacheCompletion(PacketPtr pkt); 183 184 /** Begins the switch out of the fetch stage. */ 185 void switchOut(); --- 86 unchanged lines hidden (view full) --- 272 /** Align a PC to the start of an I-cache block. */ 273 Addr icacheBlockAlignPC(Addr addr) 274 { 275 addr = TheISA::realPCToFetchPC(addr); 276 return (addr & ~(cacheBlkMask)); 277 } 278 279 private: |
280 /** Handles retrying the fetch access. */ |
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271 void recvRetry(); 272 273 /** Returns the appropriate thread to fetch, given the fetch policy. */ 274 int getFetchingThread(FetchPriority &fetch_priority); 275 276 /** Returns the appropriate thread to fetch using a round robin policy. */ 277 int roundRobin(); 278 --- 122 unchanged lines hidden (view full) --- 401 /** Checks if there is an interrupt pending. If there is, fetch 402 * must stop once it is not fetching PAL instructions. 403 */ 404 bool interruptPending; 405 406 /** Records if fetch is switched out. */ 407 bool switchedOut; 408 | 281 void recvRetry(); 282 283 /** Returns the appropriate thread to fetch, given the fetch policy. */ 284 int getFetchingThread(FetchPriority &fetch_priority); 285 286 /** Returns the appropriate thread to fetch using a round robin policy. */ 287 int roundRobin(); 288 --- 122 unchanged lines hidden (view full) --- 411 /** Checks if there is an interrupt pending. If there is, fetch 412 * must stop once it is not fetching PAL instructions. 413 */ 414 bool interruptPending; 415 416 /** Records if fetch is switched out. */ 417 bool switchedOut; 418 |
409#if !FULL_SYSTEM 410 /** Page table pointer. */ 411// PageTable *pTable; 412#endif 413 | |
414 // @todo: Consider making these vectors and tracking on a per thread basis. 415 /** Stat for total number of cycles stalled due to an icache miss. */ 416 Stats::Scalar<> icacheStallCycles; 417 /** Stat for total number of fetched instructions. */ 418 Stats::Scalar<> fetchedInsts; 419 Stats::Scalar<> fetchedBranches; 420 /** Stat for total number of predicted branches. */ 421 Stats::Scalar<> predictedBranches; --- 29 unchanged lines hidden --- | 419 // @todo: Consider making these vectors and tracking on a per thread basis. 420 /** Stat for total number of cycles stalled due to an icache miss. */ 421 Stats::Scalar<> icacheStallCycles; 422 /** Stat for total number of fetched instructions. */ 423 Stats::Scalar<> fetchedInsts; 424 Stats::Scalar<> fetchedBranches; 425 /** Stat for total number of predicted branches. */ 426 Stats::Scalar<> predictedBranches; --- 29 unchanged lines hidden --- |