1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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175 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
176
177 /** Initialize stage. */
178 void initStage();
179
180 /** Processes cache completion event. */
181 void processCacheCompletion(PacketPtr pkt);
182
183 /** Begins the switch out of the fetch stage. */
184 void switchOut();
185
186 /** Completes the switch out of the fetch stage. */
187 void doSwitchOut();
188
189 /** Takes over from another CPU's thread. */
190 void takeOverFrom();
191
192 /** Checks if the fetch stage is switched out. */
193 bool isSwitchedOut() { return switchedOut; }
194
195 /** Tells fetch to wake up from a quiesce instruction. */
196 void wakeFromQuiesce();

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416 /** Thread ID being fetched. */
417 int threadFetched;
418
419 /** Checks if there is an interrupt pending. If there is, fetch
420 * must stop once it is not fetching PAL instructions.
421 */
422 bool interruptPending;
423
424 /** Records if fetch is switched out. */
425 bool switchedOut;
426
427 // @todo: Consider making these vectors and tracking on a per thread basis.
428 /** Stat for total number of cycles stalled due to an icache miss. */
429 Stats::Scalar<> icacheStallCycles;
430 /** Stat for total number of fetched instructions. */
431 Stats::Scalar<> fetchedInsts;

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