1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// Todo: SMT fetch,
32// Add a way to get a stage's current status.
33
34#ifndef __CPU_O3_CPU_SIMPLE_FETCH_HH__
35#define __CPU_O3_CPU_SIMPLE_FETCH_HH__
36
37#include "base/statistics.hh"
38#include "base/timebuf.hh"
39#include "cpu/pc_event.hh"
40#include "mem/mem_interface.hh"
41#include "sim/eventq.hh"
42
43/**
44 * SimpleFetch class to fetch a single instruction each cycle. SimpleFetch
45 * will stall if there's an Icache miss, but otherwise assumes a one cycle
46 * Icache hit.
47 */
48
49template <class Impl>
50class SimpleFetch
51{
52 public:
53 /** Typedefs from Impl. */
54 typedef typename Impl::CPUPol CPUPol;
55 typedef typename Impl::DynInst DynInst;
56 typedef typename Impl::DynInstPtr DynInstPtr;
57 typedef typename Impl::FullCPU FullCPU;
58 typedef typename Impl::Params Params;
59
60 typedef typename CPUPol::BPredUnit BPredUnit;
61 typedef typename CPUPol::FetchStruct FetchStruct;
62 typedef typename CPUPol::TimeStruct TimeStruct;
63
64 /** Typedefs from ISA. */
65 typedef TheISA::MachInst MachInst;
66
67 public:
68 enum Status {
69 Running,
70 Idle,
71 Squashing,
72 Blocked,
73 IcacheMissStall,
74 IcacheMissComplete
75 };
76
77 // May eventually need statuses on a per thread basis.
78 Status _status;
79
80 bool stalled;
81
82 public:
83 class CacheCompletionEvent : public Event
84 {
85 private:
86 SimpleFetch *fetch;
87
88 public:
89 CacheCompletionEvent(SimpleFetch *_fetch);
90
91 virtual void process();
92 virtual const char *description();
93 };
94
95 public:
96 /** SimpleFetch constructor. */
97 SimpleFetch(Params &params);
98
99 void regStats();
100
101 void setCPU(FullCPU *cpu_ptr);
102
103 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
104
105 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
106
107 void processCacheCompletion();
108
109 private:
110 /**
111 * Looks up in the branch predictor to see if the next PC should be
112 * either next PC+=MachInst or a branch target.
113 * @param next_PC Next PC variable passed in by reference. It is
114 * expected to be set to the current PC; it will be updated with what
115 * the next PC will be.
116 * @return Whether or not a branch was predicted as taken.
117 */
118 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC);
119
120 /**
121 * Fetches the cache line that contains fetch_PC. Returns any
122 * fault that happened. Puts the data into the class variable
123 * cacheData.
124 * @param fetch_PC The PC address that is being fetched from.
125 * @return Any fault that occured.
126 */
127 Fault fetchCacheLine(Addr fetch_PC);
128
129 inline void doSquash(const Addr &new_PC);
130
131 void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num);
132
133 public:
134 // Figure out PC vs next PC and how it should be updated
135 void squash(const Addr &new_PC);
136
137 void tick();
138
139 void fetch();
140
141 // Align an address (typically a PC) to the start of an I-cache block.
142 // We fold in the PISA 64- to 32-bit conversion here as well.
143 Addr icacheBlockAlignPC(Addr addr)
144 {
145 addr = TheISA::realPCToFetchPC(addr);
146 return (addr & ~(cacheBlkMask));
147 }
148
149 private:
150 /** Pointer to the FullCPU. */
151 FullCPU *cpu;
152
153 /** Time buffer interface. */
154 TimeBuffer<TimeStruct> *timeBuffer;
155
156 /** Wire to get decode's information from backwards time buffer. */
157 typename TimeBuffer<TimeStruct>::wire fromDecode;

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167
168 /** Internal fetch instruction queue. */
169 TimeBuffer<FetchStruct> *fetchQueue;
170
171 //Might be annoying how this name is different than the queue.
172 /** Wire used to write any information heading to decode. */
173 typename TimeBuffer<FetchStruct>::wire toDecode;
174
175 /** Icache interface. */
176 MemInterface *icacheInterface;
177
178 /** BPredUnit. */
179 BPredUnit branchPred;
180
181 /** Memory request used to access cache. */
182 MemReqPtr memReq;
183
184 /** Decode to fetch delay, in ticks. */
185 unsigned decodeToFetchDelay;
186
187 /** Rename to fetch delay, in ticks. */
188 unsigned renameToFetchDelay;
189
190 /** IEW to fetch delay, in ticks. */
191 unsigned iewToFetchDelay;

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198
199 /** Cache block size. */
200 int cacheBlkSize;
201
202 /** Mask to get a cache block's address. */
203 Addr cacheBlkMask;
204
205 /** The cache line being fetched. */
206 uint8_t *cacheData;
207
208 /** Size of instructions. */
209 int instSize;
210
211 /** Icache stall statistics. */
212 Counter lastIcacheStall;
213
214 Stats::Scalar<> icacheStallCycles;
215 Stats::Scalar<> fetchedInsts;
216 Stats::Scalar<> predictedBranches;
217 Stats::Scalar<> fetchCycles;
218 Stats::Scalar<> fetchSquashCycles;
219 Stats::Scalar<> fetchBlockedCycles;
220 Stats::Scalar<> fetchedCacheLines;
221
222 Stats::Distribution<> fetch_nisn_dist;
223};
224
225#endif //__CPU_O3_CPU_SIMPLE_FETCH_HH__