1/*
2 * Copyright (c) 2010-2012, 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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54#include "cpu/translation.hh"
55#include "enums/FetchPolicy.hh"
56#include "mem/packet.hh"
57#include "mem/port.hh"
58#include "sim/eventq.hh"
59#include "sim/probe/probe.hh"
60
61struct DerivO3CPUParams;
62
63/**
64 * DefaultFetch class handles both single threaded and SMT fetch. Its
65 * width is specified by the parameters; each cycle it tries to fetch
66 * that many instructions. It supports using a branch predictor to
67 * predict direction and targets.
68 * It supports the idling functionality of the CPU by indicating to
69 * the CPU when it is active and inactive.

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80
81 /** Typedefs from the CPU policy. */
82 typedef typename CPUPol::FetchStruct FetchStruct;
83 typedef typename CPUPol::TimeStruct TimeStruct;
84
85 /** Typedefs from ISA. */
86 typedef TheISA::MachInst MachInst;
87
88 class FetchTranslation : public BaseTLB::Translation
89 {
90 protected:
91 DefaultFetch<Impl> *fetch;
92
93 public:
94 FetchTranslation(DefaultFetch<Impl> *_fetch)
95 : fetch(_fetch)

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348 Addr fetchBufferAlignPC(Addr addr)
349 {
350 return (addr & ~(fetchBufferMask));
351 }
352
353 /** The decoder. */
354 TheISA::Decoder *decoder[Impl::MaxThreads];
355
356 private:
357 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
358 StaticInstPtr curMacroop, TheISA::PCState thisPC,
359 TheISA::PCState nextPC, bool trace);
360
361 /** Returns the appropriate thread to fetch, given the fetch policy. */
362 ThreadID getFetchingThread();
363

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506 /** Thread ID being fetched. */
507 ThreadID threadFetched;
508
509 /** Checks if there is an interrupt pending. If there is, fetch
510 * must stop once it is not fetching PAL instructions.
511 */
512 bool interruptPending;
513
514 /** Set to true if a pipelined I-cache request should be issued. */
515 bool issuePipelinedIfetch[Impl::MaxThreads];
516
517 /** Event used to delay fault generation of translation faults */
518 FinishTranslationEvent finishTranslationEvent;
519
520 // @todo: Consider making these vectors and tracking on a per thread basis.
521 /** Stat for total number of cycles stalled due to an icache miss. */

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