1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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80 typedef typename CPUPol::BPredUnit BPredUnit;
81 typedef typename CPUPol::FetchStruct FetchStruct;
82 typedef typename CPUPol::TimeStruct TimeStruct;
83
84 /** Typedefs from ISA. */
85 typedef TheISA::MachInst MachInst;
86 typedef TheISA::ExtMachInst ExtMachInst;
87
88 class FetchTranslation : public BaseTLB::Translation
89 {
90 protected:
91 DefaultFetch<Impl> *fetch;
92
93 public:
94 FetchTranslation(DefaultFetch<Impl> *_fetch)
95 : fetch(_fetch)

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201 DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
202
203 /** Returns the name of fetch. */
204 std::string name() const;
205
206 /** Registers statistics. */
207 void regStats();
208
209 /** Sets the main backwards communication time buffer pointer. */
210 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
211
212 /** Sets pointer to list of active threads. */
213 void setActiveThreads(std::list<ThreadID> *at_ptr);
214
215 /** Sets pointer to time buffer used to communicate to the next stage. */
216 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
217
218 /** Initialize stage. */
219 void initStage();
220
221 /** Tells the fetch stage that the Icache is set. */
222 void setIcache();
223
224 /** Handles retrying the fetch access. */
225 void recvRetry();
226
227 /** Processes cache completion event. */
228 void processCacheCompletion(PacketPtr pkt);
229
230 /** Begins the drain of the fetch stage. */
231 bool drain();
232
233 /** Resumes execution after a drain. */
234 void resume();

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342 /** The decoder. */
343 Decoder decoder;
344
345 private:
346 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
347 StaticInstPtr curMacroop, TheISA::PCState thisPC,
348 TheISA::PCState nextPC, bool trace);
349
350 /** Returns the appropriate thread to fetch, given the fetch policy. */
351 ThreadID getFetchingThread(FetchPriority &fetch_priority);
352
353 /** Returns the appropriate thread to fetch using a round robin policy. */
354 ThreadID roundRobin();
355
356 /** Returns the appropriate thread to fetch using the IQ count policy. */
357 ThreadID iqCount();

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390
391 /** Internal fetch instruction queue. */
392 TimeBuffer<FetchStruct> *fetchQueue;
393
394 //Might be annoying how this name is different than the queue.
395 /** Wire used to write any information heading to decode. */
396 typename TimeBuffer<FetchStruct>::wire toDecode;
397
398 /** BPredUnit. */
399 BPredUnit branchPred;
400
401 /** Predecoder. */
402 TheISA::Predecoder predecoder;
403
404 TheISA::PCState pc[Impl::MaxThreads];
405

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