dyn_inst_impl.hh (9046:a1104cc13db2) dyn_inst_impl.hh (9252:f350fac86d0f)
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include "base/cp_annotate.hh"
44#include "cpu/o3/dyn_inst.hh"
45#include "sim/full_system.hh"
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include "base/cp_annotate.hh"
44#include "cpu/o3/dyn_inst.hh"
45#include "sim/full_system.hh"
46#include "debug/O3PipeView.hh"
46
47template <class Impl>
48BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
49 StaticInstPtr macroop,
50 TheISA::PCState pc, TheISA::PCState predPC,
51 InstSeqNum seq_num, O3CPU *cpu)
52 : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
53{
54 initVars();
55}
56
57template <class Impl>
58BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst,
59 StaticInstPtr _macroop)
60 : BaseDynInst<Impl>(_staticInst, _macroop)
61{
62 initVars();
63}
64
47
48template <class Impl>
49BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
50 StaticInstPtr macroop,
51 TheISA::PCState pc, TheISA::PCState predPC,
52 InstSeqNum seq_num, O3CPU *cpu)
53 : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
54{
55 initVars();
56}
57
58template <class Impl>
59BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst,
60 StaticInstPtr _macroop)
61 : BaseDynInst<Impl>(_staticInst, _macroop)
62{
63 initVars();
64}
65
66template <class Impl>BaseO3DynInst<Impl>::~BaseO3DynInst()
67{
68#if TRACING_ON
69 Tick val, fetch = this->fetchTick;
70 // Print info needed by the pipeline activity viewer.
71 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
72 fetch,
73 this->instAddr(),
74 this->microPC(),
75 this->seqNum,
76 this->staticInst->disassemble(this->instAddr()));
77 val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick;
78 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val);
79 val = (this->renameTick == -1) ? 0 : fetch + this->renameTick;
80 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val);
81 val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick;
82 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val);
83 val = (this->issueTick == -1) ? 0 : fetch + this->issueTick;
84 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val);
85 val = (this->completeTick == -1) ? 0 : fetch + this->completeTick;
86 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val);
87 val = (this->commitTick == -1) ? 0 : fetch + this->commitTick;
88 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", val);
89#endif
90};
91
92
65template <class Impl>
66void
67BaseO3DynInst<Impl>::initVars()
68{
69 // Make sure to have the renamed register entries set to the same
70 // as the normal register entries. It will allow the IQ to work
71 // without any modifications.
72 for (int i = 0; i < this->staticInst->numDestRegs(); i++) {

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77 this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
78 }
79
80 this->_readySrcRegIdx.reset();
81
82 _numDestMiscRegs = 0;
83
84#if TRACING_ON
93template <class Impl>
94void
95BaseO3DynInst<Impl>::initVars()
96{
97 // Make sure to have the renamed register entries set to the same
98 // as the normal register entries. It will allow the IQ to work
99 // without any modifications.
100 for (int i = 0; i < this->staticInst->numDestRegs(); i++) {

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105 this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
106 }
107
108 this->_readySrcRegIdx.reset();
109
110 _numDestMiscRegs = 0;
111
112#if TRACING_ON
85 fetchTick = 0;
86 decodeTick = 0;
87 renameTick = 0;
88 dispatchTick = 0;
89 issueTick = 0;
90 completeTick = 0;
113 // Value -1 indicates that particular phase
114 // hasn't happened (yet).
115 fetchTick = -1;
116 decodeTick = -1;
117 renameTick = -1;
118 dispatchTick = -1;
119 issueTick = -1;
120 completeTick = -1;
121 commitTick = -1;
91#endif
92}
93
94template <class Impl>
95Fault
96BaseO3DynInst<Impl>::execute()
97{
98 // @todo: Pretty convoluted way to avoid squashing from happening

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123}
124
125template <class Impl>
126Fault
127BaseO3DynInst<Impl>::execute()
128{
129 // @todo: Pretty convoluted way to avoid squashing from happening

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