dyn_inst_impl.hh (8733:64a7bf8fa56c) | dyn_inst_impl.hh (8779:2a590c51adb1) |
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1/* | 1/* |
2 * Copyright (c) 2010-2011 ARM Limited | 2 * Copyright (c) 2010 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 25 unchanged lines hidden (view full) --- 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#include "base/cp_annotate.hh" | 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 25 unchanged lines hidden (view full) --- 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#include "base/cp_annotate.hh" |
44#include "config/use_checker.hh" | |
45#include "cpu/o3/dyn_inst.hh" | 44#include "cpu/o3/dyn_inst.hh" |
45#include "sim/full_system.hh" |
|
46 47template <class Impl> 48BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst, 49 StaticInstPtr macroop, 50 TheISA::PCState pc, TheISA::PCState predPC, 51 InstSeqNum seq_num, O3CPU *cpu) 52 : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu) 53{ --- 78 unchanged lines hidden (view full) --- 132{ 133 // @todo: Pretty convoluted way to avoid squashing from happening 134 // when using the TC during an instruction's execution 135 // (specifically for instructions that have side-effects that use 136 // the TC). Fix this. 137 bool in_syscall = this->thread->inSyscall; 138 this->thread->inSyscall = true; 139 | 46 47template <class Impl> 48BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst, 49 StaticInstPtr macroop, 50 TheISA::PCState pc, TheISA::PCState predPC, 51 InstSeqNum seq_num, O3CPU *cpu) 52 : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu) 53{ --- 78 unchanged lines hidden (view full) --- 132{ 133 // @todo: Pretty convoluted way to avoid squashing from happening 134 // when using the TC during an instruction's execution 135 // (specifically for instructions that have side-effects that use 136 // the TC). Fix this. 137 bool in_syscall = this->thread->inSyscall; 138 this->thread->inSyscall = true; 139 |
140#if USE_CHECKER 141 if (this->isStoreConditional()) { 142 this->reqToVerify->setExtraData(pkt->req->getExtraData()); 143 } 144#endif | |
145 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); 146 147 this->thread->inSyscall = in_syscall; 148 149 return this->fault; 150} 151 | 140 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); 141 142 this->thread->inSyscall = in_syscall; 143 144 return this->fault; 145} 146 |
152#if FULL_SYSTEM | |
153template <class Impl> 154Fault 155BaseO3DynInst<Impl>::hwrei() 156{ 157#if THE_ISA == ALPHA_ISA 158 // Can only do a hwrei when in pal mode. 159 if (!(this->instAddr() & 0x3)) 160 return new AlphaISA::UnimplementedOpcodeFault; --- 28 unchanged lines hidden (view full) --- 189bool 190BaseO3DynInst<Impl>::simPalCheck(int palFunc) 191{ 192#if THE_ISA != ALPHA_ISA 193 panic("simPalCheck called, but PAL only exists in Alpha!\n"); 194#endif 195 return this->cpu->simPalCheck(palFunc, this->threadNumber); 196} | 147template <class Impl> 148Fault 149BaseO3DynInst<Impl>::hwrei() 150{ 151#if THE_ISA == ALPHA_ISA 152 // Can only do a hwrei when in pal mode. 153 if (!(this->instAddr() & 0x3)) 154 return new AlphaISA::UnimplementedOpcodeFault; --- 28 unchanged lines hidden (view full) --- 183bool 184BaseO3DynInst<Impl>::simPalCheck(int palFunc) 185{ 186#if THE_ISA != ALPHA_ISA 187 panic("simPalCheck called, but PAL only exists in Alpha!\n"); 188#endif 189 return this->cpu->simPalCheck(palFunc, this->threadNumber); 190} |
197#endif | |
198 199template <class Impl> 200void 201BaseO3DynInst<Impl>::syscall(int64_t callnum) 202{ | 191 192template <class Impl> 193void 194BaseO3DynInst<Impl>::syscall(int64_t callnum) 195{ |
203#if FULL_SYSTEM 204 panic("Syscall emulation isn't available in FS mode.\n"); 205#else 206 // HACK: check CPU's nextPC before and after syscall. If it 207 // changes, update this instruction's nextPC because the syscall 208 // must have changed the nextPC. 209 TheISA::PCState curPC = this->cpu->pcState(this->threadNumber); 210 this->cpu->syscall(callnum, this->threadNumber); 211 TheISA::PCState newPC = this->cpu->pcState(this->threadNumber); 212 if (!(curPC == newPC)) { 213 this->pcState(newPC); | 196 if (FullSystem) { 197 panic("Syscall emulation isn't available in FS mode.\n"); 198 } else { 199 // HACK: check CPU's nextPC before and after syscall. If it 200 // changes, update this instruction's nextPC because the syscall 201 // must have changed the nextPC. 202 TheISA::PCState curPC = this->cpu->pcState(this->threadNumber); 203 this->cpu->syscall(callnum, this->threadNumber); 204 TheISA::PCState newPC = this->cpu->pcState(this->threadNumber); 205 if (!(curPC == newPC)) { 206 this->pcState(newPC); 207 } |
214 } | 208 } |
215#endif | |
216} 217 | 209} 210 |