dyn_inst_impl.hh (8557:f44572edfba3) dyn_inst_impl.hh (8733:64a7bf8fa56c)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include "base/cp_annotate.hh"
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include "base/cp_annotate.hh"
44#include "config/use_checker.hh"
44#include "cpu/o3/dyn_inst.hh"
45
46template <class Impl>
47BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
48 StaticInstPtr macroop,
49 TheISA::PCState pc, TheISA::PCState predPC,
50 InstSeqNum seq_num, O3CPU *cpu)
51 : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)

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131{
132 // @todo: Pretty convoluted way to avoid squashing from happening
133 // when using the TC during an instruction's execution
134 // (specifically for instructions that have side-effects that use
135 // the TC). Fix this.
136 bool in_syscall = this->thread->inSyscall;
137 this->thread->inSyscall = true;
138
45#include "cpu/o3/dyn_inst.hh"
46
47template <class Impl>
48BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
49 StaticInstPtr macroop,
50 TheISA::PCState pc, TheISA::PCState predPC,
51 InstSeqNum seq_num, O3CPU *cpu)
52 : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)

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132{
133 // @todo: Pretty convoluted way to avoid squashing from happening
134 // when using the TC during an instruction's execution
135 // (specifically for instructions that have side-effects that use
136 // the TC). Fix this.
137 bool in_syscall = this->thread->inSyscall;
138 this->thread->inSyscall = true;
139
140#if USE_CHECKER
141 if (this->isStoreConditional()) {
142 this->reqToVerify->setExtraData(pkt->req->getExtraData());
143 }
144#endif
139 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
140
141 this->thread->inSyscall = in_syscall;
142
143 return this->fault;
144}
145
146#if FULL_SYSTEM

--- 65 unchanged lines hidden --- 		145 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
146
147 this->thread->inSyscall = in_syscall;
148
149 return this->fault;
150}
151
152#if FULL_SYSTEM

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