dyn_inst_impl.hh (5640:c811ced9efc1) dyn_inst_impl.hh (5702:bf84e2fa05f7)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 111 unchanged lines hidden (view full) ---

120{
121 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
122
123 return this->fault;
124}
125
126#if FULL_SYSTEM
127template <class Impl>
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 111 unchanged lines hidden (view full) ---

120{
121 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
122
123 return this->fault;
124}
125
126#if FULL_SYSTEM
127template <class Impl>
128Fault
129BaseO3DynInst<Impl>::hwrei()
130{
131#if THE_ISA == ALPHA_ISA
132 // Can only do a hwrei when in pal mode.
133 if (!(this->readPC() & 0x3))
134 return new AlphaISA::UnimplementedOpcodeFault;
135
136 // Set the next PC based on the value of the EXC_ADDR IPR.
137 this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
138 this->threadNumber));
139
140 // Tell CPU to clear any state it needs to if a hwrei is taken.
141 this->cpu->hwrei(this->threadNumber);
142#else
143
144#endif
145 // FIXME: XXX check for interrupts? XXX
146 return NoFault;
147}
148
149template <class Impl>
128void
129BaseO3DynInst<Impl>::trap(Fault fault)
130{
131 this->cpu->trap(fault, this->threadNumber);
132}
150void
151BaseO3DynInst<Impl>::trap(Fault fault)
152{
153 this->cpu->trap(fault, this->threadNumber);
154}
155
156template <class Impl>
157bool
158BaseO3DynInst<Impl>::simPalCheck(int palFunc)
159{
160#if THE_ISA != ALPHA_ISA
161 panic("simPalCheck called, but PAL only exists in Alpha!\n");
162#endif
163 return this->cpu->simPalCheck(palFunc, this->threadNumber);
164}
133#else
134template <class Impl>
135void
136BaseO3DynInst<Impl>::syscall(int64_t callnum)
137{
138 // HACK: check CPU's nextPC before and after syscall. If it
139 // changes, update this instruction's nextPC because the syscall
140 // must have changed the nextPC.
141 Addr cpu_next_pc = this->cpu->readNextPC(this->threadNumber);
142 this->cpu->syscall(callnum, this->threadNumber);
143 Addr new_next_pc = this->cpu->readNextPC(this->threadNumber);
144 if (cpu_next_pc != new_next_pc) {
145 this->setNextPC(new_next_pc);
146 }
147}
148#endif
149
165#else
166template <class Impl>
167void
168BaseO3DynInst<Impl>::syscall(int64_t callnum)
169{
170 // HACK: check CPU's nextPC before and after syscall. If it
171 // changes, update this instruction's nextPC because the syscall
172 // must have changed the nextPC.
173 Addr cpu_next_pc = this->cpu->readNextPC(this->threadNumber);
174 this->cpu->syscall(callnum, this->threadNumber);
175 Addr new_next_pc = this->cpu->readNextPC(this->threadNumber);
176 if (cpu_next_pc != new_next_pc) {
177 this->setNextPC(new_next_pc);
178 }
179}
180#endif
181