1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
| 1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
|
43#include "base/cp_annotate.hh"
44#include "cpu/o3/dyn_inst.hh"
45#include "sim/full_system.hh"
46#include "debug/O3PipeView.hh"
47
48template <class Impl>
49BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
50 StaticInstPtr macroop,
51 TheISA::PCState pc, TheISA::PCState predPC,
52 InstSeqNum seq_num, O3CPU *cpu)
53 : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
54{
55 initVars();
56}
57
58template <class Impl>
59BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst,
60 StaticInstPtr _macroop)
61 : BaseDynInst<Impl>(_staticInst, _macroop)
62{
63 initVars();
64}
65
66template <class Impl>BaseO3DynInst<Impl>::~BaseO3DynInst()
67{
68#if TRACING_ON
69 if (DTRACE(O3PipeView)) {
70 Tick fetch = this->fetchTick;
71 // fetchTick can be -1 if the instruction fetched outside the trace window.
72 if (fetch != -1) {
73 Tick val;
74 // Print info needed by the pipeline activity viewer.
75 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
76 fetch,
77 this->instAddr(),
78 this->microPC(),
79 this->seqNum,
80 this->staticInst->disassemble(this->instAddr()));
81
82 val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick;
83 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val);
84 val = (this->renameTick == -1) ? 0 : fetch + this->renameTick;
85 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val);
86 val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick;
87 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val);
88 val = (this->issueTick == -1) ? 0 : fetch + this->issueTick;
89 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val);
90 val = (this->completeTick == -1) ? 0 : fetch + this->completeTick;
91 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val);
92 val = (this->commitTick == -1) ? 0 : fetch + this->commitTick;
93
94 Tick valS = (this->storeTick == -1) ? 0 : fetch + this->storeTick;
95 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu:store:%llu\n", val, valS);
96 }
97 }
98#endif
99};
100
101
102template <class Impl>
103void
104BaseO3DynInst<Impl>::initVars()
105{
106 // Make sure to have the renamed register entries set to the same
107 // as the normal register entries. It will allow the IQ to work
108 // without any modifications.
109 for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
110 this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
111 }
112
113 for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
114 this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
115 }
116
117 this->_readySrcRegIdx.reset();
118
119 _numDestMiscRegs = 0;
120
121#if TRACING_ON
122 // Value -1 indicates that particular phase
123 // hasn't happened (yet).
124 fetchTick = -1;
125 decodeTick = -1;
126 renameTick = -1;
127 dispatchTick = -1;
128 issueTick = -1;
129 completeTick = -1;
130 commitTick = -1;
131 storeTick = -1;
132#endif
133}
134
135template <class Impl>
136Fault
137BaseO3DynInst<Impl>::execute()
138{
139 // @todo: Pretty convoluted way to avoid squashing from happening
140 // when using the TC during an instruction's execution
141 // (specifically for instructions that have side-effects that use
142 // the TC). Fix this.
143 bool no_squash_from_TC = this->thread->noSquashFromTC;
144 this->thread->noSquashFromTC = true;
145
146 this->fault = this->staticInst->execute(this, this->traceData);
147
148 this->thread->noSquashFromTC = no_squash_from_TC;
149
150 return this->fault;
151}
152
153template <class Impl>
154Fault
155BaseO3DynInst<Impl>::initiateAcc()
156{
157 // @todo: Pretty convoluted way to avoid squashing from happening
158 // when using the TC during an instruction's execution
159 // (specifically for instructions that have side-effects that use
160 // the TC). Fix this.
161 bool no_squash_from_TC = this->thread->noSquashFromTC;
162 this->thread->noSquashFromTC = true;
163
164 this->fault = this->staticInst->initiateAcc(this, this->traceData);
165
166 this->thread->noSquashFromTC = no_squash_from_TC;
167
168 return this->fault;
169}
170
171template <class Impl>
172Fault
173BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
174{
175 // @todo: Pretty convoluted way to avoid squashing from happening
176 // when using the TC during an instruction's execution
177 // (specifically for instructions that have side-effects that use
178 // the TC). Fix this.
179 bool no_squash_from_TC = this->thread->noSquashFromTC;
180 this->thread->noSquashFromTC = true;
181
182 if (this->cpu->checker) {
183 if (this->isStoreConditional()) {
184 this->reqToVerify->setExtraData(pkt->req->getExtraData());
185 }
186 }
187
188 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
189
190 this->thread->noSquashFromTC = no_squash_from_TC;
191
192 return this->fault;
193}
194
195template <class Impl>
196Fault
197BaseO3DynInst<Impl>::hwrei()
198{
199#if THE_ISA == ALPHA_ISA
200 // Can only do a hwrei when in pal mode.
201 if (!(this->instAddr() & 0x3))
202 return new AlphaISA::UnimplementedOpcodeFault;
203
204 // Set the next PC based on the value of the EXC_ADDR IPR.
205 AlphaISA::PCState pc = this->pcState();
206 pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
207 this->threadNumber));
208 this->pcState(pc);
209 if (CPA::available()) {
210 ThreadContext *tc = this->cpu->tcBase(this->threadNumber);
211 CPA::cpa()->swAutoBegin(tc, this->nextInstAddr());
212 }
213
214 // Tell CPU to clear any state it needs to if a hwrei is taken.
215 this->cpu->hwrei(this->threadNumber);
216#else
217
218#endif
219 // FIXME: XXX check for interrupts? XXX
220 return NoFault;
221}
222
223template <class Impl>
224void
225BaseO3DynInst<Impl>::trap(Fault fault)
226{
227 this->cpu->trap(fault, this->threadNumber, this->staticInst);
228}
229
230template <class Impl>
231bool
232BaseO3DynInst<Impl>::simPalCheck(int palFunc)
233{
234#if THE_ISA != ALPHA_ISA
235 panic("simPalCheck called, but PAL only exists in Alpha!\n");
236#endif
237 return this->cpu->simPalCheck(palFunc, this->threadNumber);
238}
239
240template <class Impl>
241void
242BaseO3DynInst<Impl>::syscall(int64_t callnum)
243{
244 if (FullSystem)
245 panic("Syscall emulation isn't available in FS mode.\n");
246
247 // HACK: check CPU's nextPC before and after syscall. If it
248 // changes, update this instruction's nextPC because the syscall
249 // must have changed the nextPC.
250 TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
251 this->cpu->syscall(callnum, this->threadNumber);
252 TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
253 if (!(curPC == newPC)) {
254 this->pcState(newPC);
255 }
256}
257
| 46#include "base/cp_annotate.hh"
47#include "cpu/o3/dyn_inst.hh"
48#include "sim/full_system.hh"
49#include "debug/O3PipeView.hh"
50
51template <class Impl>
52BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
53 StaticInstPtr macroop,
54 TheISA::PCState pc, TheISA::PCState predPC,
55 InstSeqNum seq_num, O3CPU *cpu)
56 : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
57{
58 initVars();
59}
60
61template <class Impl>
62BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst,
63 StaticInstPtr _macroop)
64 : BaseDynInst<Impl>(_staticInst, _macroop)
65{
66 initVars();
67}
68
69template <class Impl>BaseO3DynInst<Impl>::~BaseO3DynInst()
70{
71#if TRACING_ON
72 if (DTRACE(O3PipeView)) {
73 Tick fetch = this->fetchTick;
74 // fetchTick can be -1 if the instruction fetched outside the trace window.
75 if (fetch != -1) {
76 Tick val;
77 // Print info needed by the pipeline activity viewer.
78 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
79 fetch,
80 this->instAddr(),
81 this->microPC(),
82 this->seqNum,
83 this->staticInst->disassemble(this->instAddr()));
84
85 val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick;
86 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val);
87 val = (this->renameTick == -1) ? 0 : fetch + this->renameTick;
88 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val);
89 val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick;
90 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val);
91 val = (this->issueTick == -1) ? 0 : fetch + this->issueTick;
92 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val);
93 val = (this->completeTick == -1) ? 0 : fetch + this->completeTick;
94 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val);
95 val = (this->commitTick == -1) ? 0 : fetch + this->commitTick;
96
97 Tick valS = (this->storeTick == -1) ? 0 : fetch + this->storeTick;
98 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu:store:%llu\n", val, valS);
99 }
100 }
101#endif
102};
103
104
105template <class Impl>
106void
107BaseO3DynInst<Impl>::initVars()
108{
109 // Make sure to have the renamed register entries set to the same
110 // as the normal register entries. It will allow the IQ to work
111 // without any modifications.
112 for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
113 this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
114 }
115
116 for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
117 this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
118 }
119
120 this->_readySrcRegIdx.reset();
121
122 _numDestMiscRegs = 0;
123
124#if TRACING_ON
125 // Value -1 indicates that particular phase
126 // hasn't happened (yet).
127 fetchTick = -1;
128 decodeTick = -1;
129 renameTick = -1;
130 dispatchTick = -1;
131 issueTick = -1;
132 completeTick = -1;
133 commitTick = -1;
134 storeTick = -1;
135#endif
136}
137
138template <class Impl>
139Fault
140BaseO3DynInst<Impl>::execute()
141{
142 // @todo: Pretty convoluted way to avoid squashing from happening
143 // when using the TC during an instruction's execution
144 // (specifically for instructions that have side-effects that use
145 // the TC). Fix this.
146 bool no_squash_from_TC = this->thread->noSquashFromTC;
147 this->thread->noSquashFromTC = true;
148
149 this->fault = this->staticInst->execute(this, this->traceData);
150
151 this->thread->noSquashFromTC = no_squash_from_TC;
152
153 return this->fault;
154}
155
156template <class Impl>
157Fault
158BaseO3DynInst<Impl>::initiateAcc()
159{
160 // @todo: Pretty convoluted way to avoid squashing from happening
161 // when using the TC during an instruction's execution
162 // (specifically for instructions that have side-effects that use
163 // the TC). Fix this.
164 bool no_squash_from_TC = this->thread->noSquashFromTC;
165 this->thread->noSquashFromTC = true;
166
167 this->fault = this->staticInst->initiateAcc(this, this->traceData);
168
169 this->thread->noSquashFromTC = no_squash_from_TC;
170
171 return this->fault;
172}
173
174template <class Impl>
175Fault
176BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
177{
178 // @todo: Pretty convoluted way to avoid squashing from happening
179 // when using the TC during an instruction's execution
180 // (specifically for instructions that have side-effects that use
181 // the TC). Fix this.
182 bool no_squash_from_TC = this->thread->noSquashFromTC;
183 this->thread->noSquashFromTC = true;
184
185 if (this->cpu->checker) {
186 if (this->isStoreConditional()) {
187 this->reqToVerify->setExtraData(pkt->req->getExtraData());
188 }
189 }
190
191 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
192
193 this->thread->noSquashFromTC = no_squash_from_TC;
194
195 return this->fault;
196}
197
198template <class Impl>
199Fault
200BaseO3DynInst<Impl>::hwrei()
201{
202#if THE_ISA == ALPHA_ISA
203 // Can only do a hwrei when in pal mode.
204 if (!(this->instAddr() & 0x3))
205 return new AlphaISA::UnimplementedOpcodeFault;
206
207 // Set the next PC based on the value of the EXC_ADDR IPR.
208 AlphaISA::PCState pc = this->pcState();
209 pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
210 this->threadNumber));
211 this->pcState(pc);
212 if (CPA::available()) {
213 ThreadContext *tc = this->cpu->tcBase(this->threadNumber);
214 CPA::cpa()->swAutoBegin(tc, this->nextInstAddr());
215 }
216
217 // Tell CPU to clear any state it needs to if a hwrei is taken.
218 this->cpu->hwrei(this->threadNumber);
219#else
220
221#endif
222 // FIXME: XXX check for interrupts? XXX
223 return NoFault;
224}
225
226template <class Impl>
227void
228BaseO3DynInst<Impl>::trap(Fault fault)
229{
230 this->cpu->trap(fault, this->threadNumber, this->staticInst);
231}
232
233template <class Impl>
234bool
235BaseO3DynInst<Impl>::simPalCheck(int palFunc)
236{
237#if THE_ISA != ALPHA_ISA
238 panic("simPalCheck called, but PAL only exists in Alpha!\n");
239#endif
240 return this->cpu->simPalCheck(palFunc, this->threadNumber);
241}
242
243template <class Impl>
244void
245BaseO3DynInst<Impl>::syscall(int64_t callnum)
246{
247 if (FullSystem)
248 panic("Syscall emulation isn't available in FS mode.\n");
249
250 // HACK: check CPU's nextPC before and after syscall. If it
251 // changes, update this instruction's nextPC because the syscall
252 // must have changed the nextPC.
253 TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
254 this->cpu->syscall(callnum, this->threadNumber);
255 TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
256 if (!(curPC == newPC)) {
257 this->pcState(newPC);
258 }
259}
260
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