1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include "base/cp_annotate.hh"
44#include "cpu/o3/dyn_inst.hh"
45
46template <class Impl>
47BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
48 TheISA::PCState pc, TheISA::PCState predPC,
49 InstSeqNum seq_num, O3CPU *cpu)
50 : BaseDynInst<Impl>(staticInst, pc, predPC, seq_num, cpu)
51{
52 initVars();
53}
54
55template <class Impl>
56BaseO3DynInst<Impl>::BaseO3DynInst(ExtMachInst inst,
57 TheISA::PCState pc, TheISA::PCState predPC,
58 InstSeqNum seq_num, O3CPU *cpu)
59 : BaseDynInst<Impl>(inst, pc, predPC, seq_num, cpu)
60{
61 initVars();
62}
63
64template <class Impl>
65BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr &_staticInst)
66 : BaseDynInst<Impl>(_staticInst)
67{
68 initVars();
69}
70
71template <class Impl>
72void
73BaseO3DynInst<Impl>::initVars()
74{
75 // Make sure to have the renamed register entries set to the same
76 // as the normal register entries. It will allow the IQ to work
77 // without any modifications.
78 for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
79 this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
80 }
81
82 for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
83 this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
84 this->_readySrcRegIdx[i] = 0;
85 }
86
87 _numDestMiscRegs = 0;
88}
89
90template <class Impl>
91Fault
92BaseO3DynInst<Impl>::execute()
93{
94 // @todo: Pretty convoluted way to avoid squashing from happening
95 // when using the TC during an instruction's execution
96 // (specifically for instructions that have side-effects that use
97 // the TC). Fix this.
98 bool in_syscall = this->thread->inSyscall;
99 this->thread->inSyscall = true;
100
101 this->fault = this->staticInst->execute(this, this->traceData);
102
103 this->thread->inSyscall = in_syscall;
104
105 return this->fault;
106}
107
108template <class Impl>
109Fault
110BaseO3DynInst<Impl>::initiateAcc()
111{
112 // @todo: Pretty convoluted way to avoid squashing from happening
113 // when using the TC during an instruction's execution
114 // (specifically for instructions that have side-effects that use
115 // the TC). Fix this.
116 bool in_syscall = this->thread->inSyscall;
117 this->thread->inSyscall = true;
118
119 this->fault = this->staticInst->initiateAcc(this, this->traceData);
120
121 this->thread->inSyscall = in_syscall;
122
123 return this->fault;
124}
125
126template <class Impl>
127Fault
128BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
129{
130 // @todo: Pretty convoluted way to avoid squashing from happening
131 // when using the TC during an instruction's execution
132 // (specifically for instructions that have side-effects that use
133 // the TC). Fix this.
134 bool in_syscall = this->thread->inSyscall;
135 this->thread->inSyscall = true;
136
137 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
138
139 this->thread->inSyscall = in_syscall;
140
141 return this->fault;
142}
143
144#if FULL_SYSTEM
145template <class Impl>
146Fault
147BaseO3DynInst<Impl>::hwrei()
148{
149#if THE_ISA == ALPHA_ISA
150 // Can only do a hwrei when in pal mode.
151 if (!(this->instAddr() & 0x3))
152 return new AlphaISA::UnimplementedOpcodeFault;
153
154 // Set the next PC based on the value of the EXC_ADDR IPR.
155 AlphaISA::PCState pc = this->pcState();
156 pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
157 this->threadNumber));
158 this->pcState(pc);
159 if (CPA::available()) {
160 ThreadContext *tc = this->cpu->tcBase(this->threadNumber);
161 CPA::cpa()->swAutoBegin(tc, this->nextInstAddr());
162 }
163
164 // Tell CPU to clear any state it needs to if a hwrei is taken.
165 this->cpu->hwrei(this->threadNumber);
166#else
167
168#endif
169 // FIXME: XXX check for interrupts? XXX
170 return NoFault;
171}
172
173template <class Impl>
174void
175BaseO3DynInst<Impl>::trap(Fault fault)
176{
177 this->cpu->trap(fault, this->threadNumber, this->staticInst);
178}
179
180template <class Impl>
181bool
182BaseO3DynInst<Impl>::simPalCheck(int palFunc)
183{
184#if THE_ISA != ALPHA_ISA
185 panic("simPalCheck called, but PAL only exists in Alpha!\n");
186#endif
187 return this->cpu->simPalCheck(palFunc, this->threadNumber);
188}
189#else
190template <class Impl>
191void
192BaseO3DynInst<Impl>::syscall(int64_t callnum)
193{
194 // HACK: check CPU's nextPC before and after syscall. If it
195 // changes, update this instruction's nextPC because the syscall
196 // must have changed the nextPC.
197 TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
198 this->cpu->syscall(callnum, this->threadNumber);
199 TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
200 if (!(curPC == newPC)) {
201 this->pcState(newPC);
202 }
203}
204#endif
205