1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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120{
121 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
122
123 return this->fault;
124}
125
126#if FULL_SYSTEM
127template <class Impl>
128void
129BaseO3DynInst<Impl>::trap(Fault fault)
130{
131 this->cpu->trap(fault, this->threadNumber);
132}
133#else
134template <class Impl>
135void
136BaseO3DynInst<Impl>::syscall(int64_t callnum)
137{
138 // HACK: check CPU's nextPC before and after syscall. If it
139 // changes, update this instruction's nextPC because the syscall
140 // must have changed the nextPC.
141 Addr cpu_next_pc = this->cpu->readNextPC(this->threadNumber);
142 this->cpu->syscall(callnum, this->threadNumber);
143 Addr new_next_pc = this->cpu->readNextPC(this->threadNumber);
144 if (cpu_next_pc != new_next_pc) {
145 this->setNextPC(new_next_pc);
146 }
147}
148#endif
149