dyn_inst.hh (9918:2c7219e2d999) dyn_inst.hh (9920:028e4da64b42)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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73 /** Extended machine instruction type. */
74 typedef TheISA::ExtMachInst ExtMachInst;
75 /** Logical register index type. */
76 typedef TheISA::RegIndex RegIndex;
77 /** Integer register index type. */
78 typedef TheISA::IntReg IntReg;
79 typedef TheISA::FloatReg FloatReg;
80 typedef TheISA::FloatRegBits FloatRegBits;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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73 /** Extended machine instruction type. */
74 typedef TheISA::ExtMachInst ExtMachInst;
75 /** Logical register index type. */
76 typedef TheISA::RegIndex RegIndex;
77 /** Integer register index type. */
78 typedef TheISA::IntReg IntReg;
79 typedef TheISA::FloatReg FloatReg;
80 typedef TheISA::FloatRegBits FloatRegBits;
81#ifdef ISA_HAS_CC_REGS
82 typedef TheISA::CCReg CCReg;
83#endif
81 /** Misc register index type. */
82 typedef TheISA::MiscReg MiscReg;
83
84 enum {
85 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
86 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
87 };
88

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217 case IntRegClass:
218 this->setIntRegOperand(this->staticInst.get(), idx,
219 this->cpu->readIntReg(prev_phys_reg));
220 break;
221 case FloatRegClass:
222 this->setFloatRegOperandBits(this->staticInst.get(), idx,
223 this->cpu->readFloatRegBits(prev_phys_reg));
224 break;
84 /** Misc register index type. */
85 typedef TheISA::MiscReg MiscReg;
86
87 enum {
88 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
89 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
90 };
91

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220 case IntRegClass:
221 this->setIntRegOperand(this->staticInst.get(), idx,
222 this->cpu->readIntReg(prev_phys_reg));
223 break;
224 case FloatRegClass:
225 this->setFloatRegOperandBits(this->staticInst.get(), idx,
226 this->cpu->readFloatRegBits(prev_phys_reg));
227 break;
228 case CCRegClass:
229 this->setCCRegOperand(this->staticInst.get(), idx,
230 this->cpu->readCCReg(prev_phys_reg));
231 break;
225 case MiscRegClass:
226 // no need to forward misc reg values
227 break;
228 }
229 }
230 }
231 /** Calls hardware return from error interrupt. */
232 Fault hwrei();

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260 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
261 }
262
263 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
264 {
265 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
266 }
267
232 case MiscRegClass:
233 // no need to forward misc reg values
234 break;
235 }
236 }
237 }
238 /** Calls hardware return from error interrupt. */
239 Fault hwrei();

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267 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
268 }
269
270 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
271 {
272 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
273 }
274
275 uint64_t readCCRegOperand(const StaticInst *si, int idx)
276 {
277 return this->cpu->readCCReg(this->_srcRegIdx[idx]);
278 }
279
268 /** @todo: Make results into arrays so they can handle multiple dest
269 * registers.
270 */
271 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
272 {
273 this->cpu->setIntReg(this->_destRegIdx[idx], val);
274 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
275 }

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282
283 void setFloatRegOperandBits(const StaticInst *si, int idx,
284 FloatRegBits val)
285 {
286 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
287 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
288 }
289
280 /** @todo: Make results into arrays so they can handle multiple dest
281 * registers.
282 */
283 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
284 {
285 this->cpu->setIntReg(this->_destRegIdx[idx], val);
286 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
287 }

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294
295 void setFloatRegOperandBits(const StaticInst *si, int idx,
296 FloatRegBits val)
297 {
298 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
299 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
300 }
301
302 void setCCRegOperand(const StaticInst *si, int idx, uint64_t val)
303 {
304 this->cpu->setCCReg(this->_destRegIdx[idx], val);
305 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
306 }
307
290#if THE_ISA == MIPS_ISA
291 uint64_t readRegOtherThread(int misc_reg)
292 {
293 panic("MIPS MT not defined for O3 CPU.\n");
294 return 0;
295 }
296
297 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)

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309 uint64_t readRegOtherThread(int misc_reg)
310 {
311 panic("MIPS MT not defined for O3 CPU.\n");
312 return 0;
313 }
314
315 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)

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