dyn_inst.hh (9046:a1104cc13db2) dyn_inst.hh (9252:f350fac86d0f)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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88 /** BaseDynInst constructor given a binary instruction. */
89 BaseO3DynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
90 TheISA::PCState pc, TheISA::PCState predPC,
91 InstSeqNum seq_num, O3CPU *cpu);
92
93 /** BaseDynInst constructor given a static inst pointer. */
94 BaseO3DynInst(StaticInstPtr _staticInst, StaticInstPtr _macroop);
95
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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88 /** BaseDynInst constructor given a binary instruction. */
89 BaseO3DynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
90 TheISA::PCState pc, TheISA::PCState predPC,
91 InstSeqNum seq_num, O3CPU *cpu);
92
93 /** BaseDynInst constructor given a static inst pointer. */
94 BaseO3DynInst(StaticInstPtr _staticInst, StaticInstPtr _macroop);
95
96 ~BaseO3DynInst();
97
96 /** Executes the instruction.*/
97 Fault execute();
98
99 /** Initiates the access. Only valid for memory operations. */
100 Fault initiateAcc();
101
102 /** Completes the access. Only valid for memory operations. */
103 Fault completeAcc(PacketPtr pkt);

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118
119 /** Number of destination misc. registers. */
120 uint8_t _numDestMiscRegs;
121
122
123 public:
124#if TRACING_ON
125 /** Tick records used for the pipeline activity viewer. */
98 /** Executes the instruction.*/
99 Fault execute();
100
101 /** Initiates the access. Only valid for memory operations. */
102 Fault initiateAcc();
103
104 /** Completes the access. Only valid for memory operations. */
105 Fault completeAcc(PacketPtr pkt);

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120
121 /** Number of destination misc. registers. */
122 uint8_t _numDestMiscRegs;
123
124
125 public:
126#if TRACING_ON
127 /** Tick records used for the pipeline activity viewer. */
126 Tick fetchTick;
127 uint32_t decodeTick;
128 uint32_t renameTick;
129 uint32_t dispatchTick;
130 uint32_t issueTick;
131 uint32_t completeTick;
128 Tick fetchTick; // instruction fetch is completed.
129 int32_t decodeTick; // instruction enters decode phase
130 int32_t renameTick; // instruction enters rename phase
131 int32_t dispatchTick;
132 int32_t issueTick;
133 int32_t completeTick;
134 int32_t commitTick;
132#endif
133
134 /** Reads a misc. register, including any side-effects the read
135 * might have as defined by the architecture.
136 */
137 MiscReg readMiscReg(int misc_reg)
138 {
139 return this->cpu->readMiscReg(misc_reg, this->threadNumber);

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136
137 /** Reads a misc. register, including any side-effects the read
138 * might have as defined by the architecture.
139 */
140 MiscReg readMiscReg(int misc_reg)
141 {
142 return this->cpu->readMiscReg(misc_reg, this->threadNumber);

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