dyn_inst.hh (8902:75b524b64c28) dyn_inst.hh (9046:a1104cc13db2)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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102 /** Completes the access. Only valid for memory operations. */
103 Fault completeAcc(PacketPtr pkt);
104
105 private:
106 /** Initializes variables. */
107 void initVars();
108
109 protected:
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 93 unchanged lines hidden (view full) ---

102 /** Completes the access. Only valid for memory operations. */
103 Fault completeAcc(PacketPtr pkt);
104
105 private:
106 /** Initializes variables. */
107 void initVars();
108
109 protected:
110 /** Values to be written to the destination misc. registers. */
111 MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs];
112
110 /** Indexes of the destination misc. registers. They are needed to defer
111 * the write accesses to the misc. registers until the commit stage, when
112 * the instruction is out of its speculative state.
113 */
113 /** Indexes of the destination misc. registers. They are needed to defer
114 * the write accesses to the misc. registers until the commit stage, when
115 * the instruction is out of its speculative state.
116 */
114 int _destMiscRegIdx[MaxInstDestRegs];
115 /** Values to be written to the destination misc. registers. */
116 MiscReg _destMiscRegVal[MaxInstDestRegs];
117 short _destMiscRegIdx[TheISA::MaxMiscDestRegs];
118
117 /** Number of destination misc. registers. */
119 /** Number of destination misc. registers. */
118 int _numDestMiscRegs;
120 uint8_t _numDestMiscRegs;
119
121
120 public:
121
122
123 public:
122#if TRACING_ON
123 /** Tick records used for the pipeline activity viewer. */
124 Tick fetchTick;
124#if TRACING_ON
125 /** Tick records used for the pipeline activity viewer. */
126 Tick fetchTick;
125 Tick decodeTick;
126 Tick renameTick;
127 Tick dispatchTick;
128 Tick issueTick;
129 Tick completeTick;
127 uint32_t decodeTick;
128 uint32_t renameTick;
129 uint32_t dispatchTick;
130 uint32_t issueTick;
131 uint32_t completeTick;
130#endif
131
132 /** Reads a misc. register, including any side-effects the read
133 * might have as defined by the architecture.
134 */
135 MiscReg readMiscReg(int misc_reg)
136 {
137 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
138 }
139
140 /** Sets a misc. register, including any side-effects the write
141 * might have as defined by the architecture.
142 */
143 void setMiscReg(int misc_reg, const MiscReg &val)
144 {
145 /** Writes to misc. registers are recorded and deferred until the
146 * commit stage, when updateMiscRegs() is called.
147 */
132#endif
133
134 /** Reads a misc. register, including any side-effects the read
135 * might have as defined by the architecture.
136 */
137 MiscReg readMiscReg(int misc_reg)
138 {
139 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
140 }
141
142 /** Sets a misc. register, including any side-effects the write
143 * might have as defined by the architecture.
144 */
145 void setMiscReg(int misc_reg, const MiscReg &val)
146 {
147 /** Writes to misc. registers are recorded and deferred until the
148 * commit stage, when updateMiscRegs() is called.
149 */
150 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
148 _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
149 _destMiscRegVal[_numDestMiscRegs] = val;
150 _numDestMiscRegs++;
151 }
152
153 /** Reads a misc. register, including any side-effects the read
154 * might have as defined by the architecture.
155 */

--- 140 unchanged lines hidden --- 		151 _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
152 _destMiscRegVal[_numDestMiscRegs] = val;
153 _numDestMiscRegs++;
154 }
155
156 /** Reads a misc. register, including any side-effects the read
157 * might have as defined by the architecture.
158 */

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