dyn_inst.hh (7720:65d338a8dba4) dyn_inst.hh (7783:9b880b40ac10)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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94
95 /** Completes the access. Only valid for memory operations. */
96 Fault completeAcc(PacketPtr pkt);
97
98 private:
99 /** Initializes variables. */
100 void initVars();
101
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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106
107 /** Completes the access. Only valid for memory operations. */
108 Fault completeAcc(PacketPtr pkt);
109
110 private:
111 /** Initializes variables. */
112 void initVars();
113
102 public:
103 /** Reads a miscellaneous register. */
104 MiscReg readMiscRegNoEffect(int misc_reg)
105 {
106 return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber);
107 }
114 protected:
115 /** Indexes of the destination misc. registers. They are needed to defer
116 * the write accesses to the misc. registers until the commit stage, when
117 * the instruction is out of its speculative state.
118 */
119 int _destMiscRegIdx[MaxInstDestRegs];
120 /** Values to be written to the destination misc. registers. */
121 MiscReg _destMiscRegVal[MaxInstDestRegs];
122 /** Number of destination misc. registers. */
123 int _numDestMiscRegs;
108
124
125 public:
109 /** Reads a misc. register, including any side-effects the read
110 * might have as defined by the architecture.
111 */
112 MiscReg readMiscReg(int misc_reg)
113 {
114 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
115 }
116
126 /** Reads a misc. register, including any side-effects the read
127 * might have as defined by the architecture.
128 */
129 MiscReg readMiscReg(int misc_reg)
130 {
131 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
132 }
133
117 /** Sets a misc. register. */
118 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
119 {
120 this->instResult.integer = val;
121 return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber);
122 }
123
124 /** Sets a misc. register, including any side-effects the write
125 * might have as defined by the architecture.
126 */
127 void setMiscReg(int misc_reg, const MiscReg &val)
128 {
134 /** Sets a misc. register, including any side-effects the write
135 * might have as defined by the architecture.
136 */
137 void setMiscReg(int misc_reg, const MiscReg &val)
138 {
129 return this->cpu->setMiscReg(misc_reg, val,
130 this->threadNumber);
139 /** Writes to misc. registers are recorded and deferred until the
140 * commit stage, when updateMiscRegs() is called.
141 */
142 _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
143 _destMiscRegVal[_numDestMiscRegs] = val;
144 _numDestMiscRegs++;
131 }
132
145 }
146
133 /** Reads a miscellaneous register. */
134 TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
135 {
136 return this->cpu->readMiscRegNoEffect(
137 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
138 this->threadNumber);
139 }
140
141 /** Reads a misc. register, including any side-effects the read
142 * might have as defined by the architecture.
143 */
144 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
145 {
146 return this->cpu->readMiscReg(
147 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
148 this->threadNumber);
149 }
150
147 /** Reads a misc. register, including any side-effects the read
148 * might have as defined by the architecture.
149 */
150 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
151 {
152 return this->cpu->readMiscReg(
153 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
154 this->threadNumber);
155 }
156
151 /** Sets a misc. register. */
152 void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val)
153 {
154 this->instResult.integer = val;
155 return this->cpu->setMiscRegNoEffect(
156 si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
157 val, this->threadNumber);
158 }
159
160 /** Sets a misc. register, including any side-effects the write
161 * might have as defined by the architecture.
162 */
163 void setMiscRegOperand(const StaticInst *si, int idx,
164 const MiscReg &val)
165 {
157 /** Sets a misc. register, including any side-effects the write
158 * might have as defined by the architecture.
159 */
160 void setMiscRegOperand(const StaticInst *si, int idx,
161 const MiscReg &val)
162 {
166 return this->cpu->setMiscReg(
167 si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
168 val, this->threadNumber);
163 int misc_reg = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
164 setMiscReg(misc_reg, val);
169 }
170
165 }
166
167 /** Called at the commit stage to update the misc. registers. */
168 void updateMiscRegs()
169 {
170 // @todo: Pretty convoluted way to avoid squashing from happening when
171 // using the TC during an instruction's execution (specifically for
172 // instructions that have side-effects that use the TC). Fix this.
173 // See cpu/o3/dyn_inst_impl.hh.
174 bool in_syscall = this->thread->inSyscall;
175 this->thread->inSyscall = true;
176
177 for (int i = 0; i < _numDestMiscRegs; i++)
178 this->cpu->setMiscReg(
179 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
180
181 this->thread->inSyscall = in_syscall;
182 }
183
171#if FULL_SYSTEM
172 /** Calls hardware return from error interrupt. */
173 Fault hwrei();
174 /** Traps to handle specified fault. */
175 void trap(Fault fault);
176 bool simPalCheck(int palFunc);
177#else
178 /** Calls a syscall. */

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185 /** Calls hardware return from error interrupt. */
186 Fault hwrei();
187 /** Traps to handle specified fault. */
188 void trap(Fault fault);
189 bool simPalCheck(int palFunc);
190#else
191 /** Calls a syscall. */

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