dyn_inst.hh (6658:f4de76601762) | dyn_inst.hh (7720:65d338a8dba4) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 60 unchanged lines hidden (view full) --- 69 70 enum { 71 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 72 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 73 }; 74 75 public: 76 /** BaseDynInst constructor given a binary instruction. */ | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 60 unchanged lines hidden (view full) --- 69 70 enum { 71 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 72 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 73 }; 74 75 public: 76 /** BaseDynInst constructor given a binary instruction. */ |
77 BaseO3DynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 78 Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, 79 InstSeqNum seq_num, O3CPU *cpu); | 77 BaseO3DynInst(StaticInstPtr staticInst, 78 TheISA::PCState pc, TheISA::PCState predPC, 79 InstSeqNum seq_num, O3CPU *cpu); |
80 81 /** BaseDynInst constructor given a binary instruction. */ | 80 81 /** BaseDynInst constructor given a binary instruction. */ |
82 BaseO3DynInst(ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 83 Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, 84 InstSeqNum seq_num, O3CPU *cpu); | 82 BaseO3DynInst(ExtMachInst inst, 83 TheISA::PCState pc, TheISA::PCState predPC, 84 InstSeqNum seq_num, O3CPU *cpu); |
85 86 /** BaseDynInst constructor given a static inst pointer. */ 87 BaseO3DynInst(StaticInstPtr &_staticInst); 88 89 /** Executes the instruction.*/ 90 Fault execute(); 91 92 /** Initiates the access. Only valid for memory operations. */ --- 174 unchanged lines hidden --- | 85 86 /** BaseDynInst constructor given a static inst pointer. */ 87 BaseO3DynInst(StaticInstPtr &_staticInst); 88 89 /** Executes the instruction.*/ 90 Fault execute(); 91 92 /** Initiates the access. Only valid for memory operations. */ --- 174 unchanged lines hidden --- |