dyn_inst.hh (13611:c8b7847b4171) dyn_inst.hh (13622:ba31c2a23eca)
1/*
2 * Copyright (c) 2010, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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61{
62 public:
63 /** Typedef for the CPU. */
64 typedef typename Impl::O3CPU O3CPU;
65
66 /** Binary machine instruction type. */
67 typedef TheISA::MachInst MachInst;
68 /** Register types. */
1/*
2 * Copyright (c) 2010, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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61{
62 public:
63 /** Typedef for the CPU. */
64 typedef typename Impl::O3CPU O3CPU;
65
66 /** Binary machine instruction type. */
67 typedef TheISA::MachInst MachInst;
68 /** Register types. */
69 typedef TheISA::CCReg CCReg;
70 using VecRegContainer = TheISA::VecRegContainer;
71 using VecElem = TheISA::VecElem;
72 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
73 using VecPredRegContainer = TheISA::VecPredRegContainer;
74
75 enum {
76 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
77 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs

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373 }
374
375 VecPredRegContainer&
376 getWritableVecPredRegOperand(const StaticInst *si, int idx) override
377 {
378 return this->cpu->getWritableVecPredReg(this->_destRegIdx[idx]);
379 }
380
69 using VecRegContainer = TheISA::VecRegContainer;
70 using VecElem = TheISA::VecElem;
71 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
72 using VecPredRegContainer = TheISA::VecPredRegContainer;
73
74 enum {
75 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
76 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs

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372 }
373
374 VecPredRegContainer&
375 getWritableVecPredRegOperand(const StaticInst *si, int idx) override
376 {
377 return this->cpu->getWritableVecPredReg(this->_destRegIdx[idx]);
378 }
379
381 CCReg readCCRegOperand(const StaticInst *si, int idx)
380 RegVal
381 readCCRegOperand(const StaticInst *si, int idx)
382 {
383 return this->cpu->readCCReg(this->_srcRegIdx[idx]);
384 }
385
386 /** @todo: Make results into arrays so they can handle multiple dest
387 * registers.
388 */
389 void

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419 void
420 setVecPredRegOperand(const StaticInst *si, int idx,
421 const VecPredRegContainer& val) override
422 {
423 this->cpu->setVecPredReg(this->_destRegIdx[idx], val);
424 BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val);
425 }
426
382 {
383 return this->cpu->readCCReg(this->_srcRegIdx[idx]);
384 }
385
386 /** @todo: Make results into arrays so they can handle multiple dest
387 * registers.
388 */
389 void

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419 void
420 setVecPredRegOperand(const StaticInst *si, int idx,
421 const VecPredRegContainer& val) override
422 {
423 this->cpu->setVecPredReg(this->_destRegIdx[idx], val);
424 BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val);
425 }
426
427 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
427 void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
428 {
429 this->cpu->setCCReg(this->_destRegIdx[idx], val);
430 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
431 }
432
433#if THE_ISA == MIPS_ISA
434 RegVal
435 readRegOtherThread(const RegId& misc_reg, ThreadID tid)

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429 this->cpu->setCCReg(this->_destRegIdx[idx], val);
430 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
431 }
432
433#if THE_ISA == MIPS_ISA
434 RegVal
435 readRegOtherThread(const RegId& misc_reg, ThreadID tid)

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