dyn_inst.hh (13582:989577bf6abc) dyn_inst.hh (13610:5d5404ac6288)
1/*
2 * Copyright (c) 2010, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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65
66 /** Binary machine instruction type. */
67 typedef TheISA::MachInst MachInst;
68 /** Register types. */
69 typedef TheISA::CCReg CCReg;
70 using VecRegContainer = TheISA::VecRegContainer;
71 using VecElem = TheISA::VecElem;
72 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
1/*
2 * Copyright (c) 2010, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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65
66 /** Binary machine instruction type. */
67 typedef TheISA::MachInst MachInst;
68 /** Register types. */
69 typedef TheISA::CCReg CCReg;
70 using VecRegContainer = TheISA::VecRegContainer;
71 using VecElem = TheISA::VecElem;
72 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
73 using VecPredRegContainer = TheISA::VecPredRegContainer;
73
74 enum {
75 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
76 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
77 };
78
79 public:
80 /** BaseDynInst constructor given a binary instruction. */

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226 case VecRegClass:
227 this->setVecRegOperand(this->staticInst.get(), idx,
228 this->cpu->readVecReg(prev_phys_reg));
229 break;
230 case VecElemClass:
231 this->setVecElemOperand(this->staticInst.get(), idx,
232 this->cpu->readVecElem(prev_phys_reg));
233 break;
74
75 enum {
76 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
77 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
78 };
79
80 public:
81 /** BaseDynInst constructor given a binary instruction. */

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227 case VecRegClass:
228 this->setVecRegOperand(this->staticInst.get(), idx,
229 this->cpu->readVecReg(prev_phys_reg));
230 break;
231 case VecElemClass:
232 this->setVecElemOperand(this->staticInst.get(), idx,
233 this->cpu->readVecElem(prev_phys_reg));
234 break;
235 case VecPredRegClass:
236 this->setVecPredRegOperand(this->staticInst.get(), idx,
237 this->cpu->readVecPredReg(prev_phys_reg));
238 break;
234 case CCRegClass:
235 this->setCCRegOperand(this->staticInst.get(), idx,
236 this->cpu->readCCReg(prev_phys_reg));
237 break;
238 case MiscRegClass:
239 // no need to forward misc reg values
240 break;
241 default:

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356 }
357 /** @} */
358
359 VecElem readVecElemOperand(const StaticInst *si, int idx) const
360 {
361 return this->cpu->readVecElem(this->_srcRegIdx[idx]);
362 }
363
239 case CCRegClass:
240 this->setCCRegOperand(this->staticInst.get(), idx,
241 this->cpu->readCCReg(prev_phys_reg));
242 break;
243 case MiscRegClass:
244 // no need to forward misc reg values
245 break;
246 default:

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361 }
362 /** @} */
363
364 VecElem readVecElemOperand(const StaticInst *si, int idx) const
365 {
366 return this->cpu->readVecElem(this->_srcRegIdx[idx]);
367 }
368
369 const VecPredRegContainer&
370 readVecPredRegOperand(const StaticInst *si, int idx) const override
371 {
372 return this->cpu->readVecPredReg(this->_srcRegIdx[idx]);
373 }
374
375 VecPredRegContainer&
376 getWritableVecPredRegOperand(const StaticInst *si, int idx) override
377 {
378 return this->cpu->getWritableVecPredReg(this->_destRegIdx[idx]);
379 }
380
364 CCReg readCCRegOperand(const StaticInst *si, int idx)
365 {
366 return this->cpu->readCCReg(this->_srcRegIdx[idx]);
367 }
368
369 /** @todo: Make results into arrays so they can handle multiple dest
370 * registers.
371 */

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394 void setVecElemOperand(const StaticInst *si, int idx,
395 const VecElem val)
396 {
397 int reg_idx = idx;
398 this->cpu->setVecElem(this->_destRegIdx[reg_idx], val);
399 BaseDynInst<Impl>::setVecElemOperand(si, idx, val);
400 }
401
381 CCReg readCCRegOperand(const StaticInst *si, int idx)
382 {
383 return this->cpu->readCCReg(this->_srcRegIdx[idx]);
384 }
385
386 /** @todo: Make results into arrays so they can handle multiple dest
387 * registers.
388 */

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411 void setVecElemOperand(const StaticInst *si, int idx,
412 const VecElem val)
413 {
414 int reg_idx = idx;
415 this->cpu->setVecElem(this->_destRegIdx[reg_idx], val);
416 BaseDynInst<Impl>::setVecElemOperand(si, idx, val);
417 }
418
419 void
420 setVecPredRegOperand(const StaticInst *si, int idx,
421 const VecPredRegContainer& val) override
422 {
423 this->cpu->setVecPredReg(this->_destRegIdx[idx], val);
424 BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val);
425 }
426
402 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
403 {
404 this->cpu->setCCReg(this->_destRegIdx[idx], val);
405 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
406 }
407
408#if THE_ISA == MIPS_ISA
409 RegVal

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428 {
429 this->cpu->setCCReg(this->_destRegIdx[idx], val);
430 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
431 }
432
433#if THE_ISA == MIPS_ISA
434 RegVal

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