dyn_inst.hh (12385:288c62455dde) dyn_inst.hh (12622:91cce46512f2)
1/*
2 * Copyright (c) 2010, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 51 unchanged lines hidden (view full) ---

60class BaseO3DynInst : public BaseDynInst<Impl>
61{
62 public:
63 /** Typedef for the CPU. */
64 typedef typename Impl::O3CPU O3CPU;
65
66 /** Binary machine instruction type. */
67 typedef TheISA::MachInst MachInst;
1/*
2 * Copyright (c) 2010, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 51 unchanged lines hidden (view full) ---

60class BaseO3DynInst : public BaseDynInst<Impl>
61{
62 public:
63 /** Typedef for the CPU. */
64 typedef typename Impl::O3CPU O3CPU;
65
66 /** Binary machine instruction type. */
67 typedef TheISA::MachInst MachInst;
68 /** Extended machine instruction type. */
69 typedef TheISA::ExtMachInst ExtMachInst;
70 /** Register types. */
71 typedef TheISA::IntReg IntReg;
72 typedef TheISA::FloatReg FloatReg;
73 typedef TheISA::FloatRegBits FloatRegBits;
74 typedef TheISA::CCReg CCReg;
75 using VecRegContainer = TheISA::VecRegContainer;
76 using VecElem = TheISA::VecElem;
77 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;

--- 358 unchanged lines hidden --- 		68 /** Register types. */
69 typedef TheISA::IntReg IntReg;
70 typedef TheISA::FloatReg FloatReg;
71 typedef TheISA::FloatRegBits FloatRegBits;
72 typedef TheISA::CCReg CCReg;
73 using VecRegContainer = TheISA::VecRegContainer;
74 using VecElem = TheISA::VecElem;
75 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;

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