dyn_inst.hh (12105:742d80361989) dyn_inst.hh (12106:7784fac1b159)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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118
119 /** Number of destination misc. registers. */
120 uint8_t _numDestMiscRegs;
121
122
123 public:
124#if TRACING_ON
125 /** Tick records used for the pipeline activity viewer. */
1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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118
119 /** Number of destination misc. registers. */
120 uint8_t _numDestMiscRegs;
121
122
123 public:
124#if TRACING_ON
125 /** Tick records used for the pipeline activity viewer. */
126 Tick fetchTick; // instruction fetch is completed.
126 Tick fetchTick; // instruction fetch is completed.
127 int32_t decodeTick; // instruction enters decode phase
128 int32_t renameTick; // instruction enters rename phase
129 int32_t dispatchTick;
130 int32_t issueTick;
131 int32_t completeTick;
132 int32_t commitTick;
133 int32_t storeTick;
134#endif

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165 _numDestMiscRegs++;
166 }
167
168 /** Reads a misc. register, including any side-effects the read
169 * might have as defined by the architecture.
170 */
171 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
172 {
127 int32_t decodeTick; // instruction enters decode phase
128 int32_t renameTick; // instruction enters rename phase
129 int32_t dispatchTick;
130 int32_t issueTick;
131 int32_t completeTick;
132 int32_t commitTick;
133 int32_t storeTick;
134#endif

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165 _numDestMiscRegs++;
166 }
167
168 /** Reads a misc. register, including any side-effects the read
169 * might have as defined by the architecture.
170 */
171 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
172 {
173 RegId reg = si->srcRegIdx(idx);
174 assert(reg.regClass == MiscRegClass);
175 return this->cpu->readMiscReg(reg.regIdx, this->threadNumber);
173 const RegId& reg = si->srcRegIdx(idx);
174 assert(reg.isMiscReg());
175 return this->cpu->readMiscReg(reg.index(), this->threadNumber);
176 }
177
178 /** Sets a misc. register, including any side-effects the write
179 * might have as defined by the architecture.
180 */
181 void setMiscRegOperand(const StaticInst *si, int idx,
182 const MiscReg &val)
183 {
176 }
177
178 /** Sets a misc. register, including any side-effects the write
179 * might have as defined by the architecture.
180 */
181 void setMiscRegOperand(const StaticInst *si, int idx,
182 const MiscReg &val)
183 {
184 RegId reg = si->destRegIdx(idx);
185 assert(reg.regClass == MiscRegClass);
186 setMiscReg(reg.regIdx, val);
184 const RegId& reg = si->destRegIdx(idx);
185 assert(reg.isMiscReg());
186 setMiscReg(reg.index(), val);
187 }
188
189 /** Called at the commit stage to update the misc. registers. */
190 void updateMiscRegs()
191 {
192 // @todo: Pretty convoluted way to avoid squashing from happening when
193 // using the TC during an instruction's execution (specifically for
194 // instructions that have side-effects that use the TC). Fix this.

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203 this->thread->noSquashFromTC = no_squash_from_TC;
204 }
205
206 void forwardOldRegs()
207 {
208
209 for (int idx = 0; idx < this->numDestRegs(); idx++) {
210 PhysRegIdPtr prev_phys_reg = this->prevDestRegIdx(idx);
187 }
188
189 /** Called at the commit stage to update the misc. registers. */
190 void updateMiscRegs()
191 {
192 // @todo: Pretty convoluted way to avoid squashing from happening when
193 // using the TC during an instruction's execution (specifically for
194 // instructions that have side-effects that use the TC). Fix this.

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203 this->thread->noSquashFromTC = no_squash_from_TC;
204 }
205
206 void forwardOldRegs()
207 {
208
209 for (int idx = 0; idx < this->numDestRegs(); idx++) {
210 PhysRegIdPtr prev_phys_reg = this->prevDestRegIdx(idx);
211 RegId original_dest_reg =
211 const RegId& original_dest_reg =
212 this->staticInst->destRegIdx(idx);
212 this->staticInst->destRegIdx(idx);
213 switch (original_dest_reg.regClass) {
213 switch (original_dest_reg.classValue()) {
214 case IntRegClass:
215 this->setIntRegOperand(this->staticInst.get(), idx,
216 this->cpu->readIntReg(prev_phys_reg));
217 break;
218 case FloatRegClass:
219 this->setFloatRegOperandBits(this->staticInst.get(), idx,
220 this->cpu->readFloatRegBits(prev_phys_reg));
221 break;

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295
296 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
297 {
298 this->cpu->setCCReg(this->_destRegIdx[idx], val);
299 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
300 }
301
302#if THE_ISA == MIPS_ISA
214 case IntRegClass:
215 this->setIntRegOperand(this->staticInst.get(), idx,
216 this->cpu->readIntReg(prev_phys_reg));
217 break;
218 case FloatRegClass:
219 this->setFloatRegOperandBits(this->staticInst.get(), idx,
220 this->cpu->readFloatRegBits(prev_phys_reg));
221 break;

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295
296 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
297 {
298 this->cpu->setCCReg(this->_destRegIdx[idx], val);
299 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
300 }
301
302#if THE_ISA == MIPS_ISA
303 MiscReg readRegOtherThread(RegId misc_reg, ThreadID tid)
303 MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid)
304 {
305 panic("MIPS MT not defined for O3 CPU.\n");
306 return 0;
307 }
308
304 {
305 panic("MIPS MT not defined for O3 CPU.\n");
306 return 0;
307 }
308
309 void setRegOtherThread(RegId misc_reg, MiscReg val, ThreadID tid)
309 void setRegOtherThread(const RegId& misc_reg, MiscReg val, ThreadID tid)
310 {
311 panic("MIPS MT not defined for O3 CPU.\n");
312 }
313#endif
314
315 public:
316 /** Calculates EA part of a memory instruction. Currently unused,
317 * though it may be useful in the future if we want to split

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311 panic("MIPS MT not defined for O3 CPU.\n");
312 }
313#endif
314
315 public:
316 /** Calculates EA part of a memory instruction. Currently unused,
317 * though it may be useful in the future if we want to split

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