dyn_inst.hh (11877:5ea85692a53e) dyn_inst.hh (12104:edd63f9c6184)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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62 public:
63 /** Typedef for the CPU. */
64 typedef typename Impl::O3CPU O3CPU;
65
66 /** Binary machine instruction type. */
67 typedef TheISA::MachInst MachInst;
68 /** Extended machine instruction type. */
69 typedef TheISA::ExtMachInst ExtMachInst;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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62 public:
63 /** Typedef for the CPU. */
64 typedef typename Impl::O3CPU O3CPU;
65
66 /** Binary machine instruction type. */
67 typedef TheISA::MachInst MachInst;
68 /** Extended machine instruction type. */
69 typedef TheISA::ExtMachInst ExtMachInst;
70 /** Logical register index type. */
71 typedef TheISA::RegIndex RegIndex;
72 /** Integer register index type. */
70 /** Register types. */
73 typedef TheISA::IntReg IntReg;
74 typedef TheISA::FloatReg FloatReg;
75 typedef TheISA::FloatRegBits FloatRegBits;
76 typedef TheISA::CCReg CCReg;
77
71 typedef TheISA::IntReg IntReg;
72 typedef TheISA::FloatReg FloatReg;
73 typedef TheISA::FloatRegBits FloatRegBits;
74 typedef TheISA::CCReg CCReg;
75
78 /** Misc register index type. */
76 /** Misc register type. */
79 typedef TheISA::MiscReg MiscReg;
80
81 enum {
82 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
83 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
84 };
85
86 public:

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167 _numDestMiscRegs++;
168 }
169
170 /** Reads a misc. register, including any side-effects the read
171 * might have as defined by the architecture.
172 */
173 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
174 {
77 typedef TheISA::MiscReg MiscReg;
78
79 enum {
80 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
81 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
82 };
83
84 public:

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165 _numDestMiscRegs++;
166 }
167
168 /** Reads a misc. register, including any side-effects the read
169 * might have as defined by the architecture.
170 */
171 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
172 {
175 return this->cpu->readMiscReg(
176 si->srcRegIdx(idx) - TheISA::Misc_Reg_Base,
177 this->threadNumber);
173 RegId reg = si->srcRegIdx(idx);
174 assert(reg.regClass == MiscRegClass);
175 return this->cpu->readMiscReg(reg.regIdx, this->threadNumber);
178 }
179
180 /** Sets a misc. register, including any side-effects the write
181 * might have as defined by the architecture.
182 */
183 void setMiscRegOperand(const StaticInst *si, int idx,
184 const MiscReg &val)
185 {
176 }
177
178 /** Sets a misc. register, including any side-effects the write
179 * might have as defined by the architecture.
180 */
181 void setMiscRegOperand(const StaticInst *si, int idx,
182 const MiscReg &val)
183 {
186 int misc_reg = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
187 setMiscReg(misc_reg, val);
184 RegId reg = si->destRegIdx(idx);
185 assert(reg.regClass == MiscRegClass);
186 setMiscReg(reg.regIdx, val);
188 }
189
190 /** Called at the commit stage to update the misc. registers. */
191 void updateMiscRegs()
192 {
193 // @todo: Pretty convoluted way to avoid squashing from happening when
194 // using the TC during an instruction's execution (specifically for
195 // instructions that have side-effects that use the TC). Fix this.

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204 this->thread->noSquashFromTC = no_squash_from_TC;
205 }
206
207 void forwardOldRegs()
208 {
209
210 for (int idx = 0; idx < this->numDestRegs(); idx++) {
211 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
187 }
188
189 /** Called at the commit stage to update the misc. registers. */
190 void updateMiscRegs()
191 {
192 // @todo: Pretty convoluted way to avoid squashing from happening when
193 // using the TC during an instruction's execution (specifically for
194 // instructions that have side-effects that use the TC). Fix this.

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203 this->thread->noSquashFromTC = no_squash_from_TC;
204 }
205
206 void forwardOldRegs()
207 {
208
209 for (int idx = 0; idx < this->numDestRegs(); idx++) {
210 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
212 TheISA::RegIndex original_dest_reg =
211 RegId original_dest_reg =
213 this->staticInst->destRegIdx(idx);
212 this->staticInst->destRegIdx(idx);
214 switch (regIdxToClass(original_dest_reg)) {
213 switch (original_dest_reg.regClass) {
215 case IntRegClass:
216 this->setIntRegOperand(this->staticInst.get(), idx,
217 this->cpu->readIntReg(prev_phys_reg));
218 break;
219 case FloatRegClass:
220 this->setFloatRegOperandBits(this->staticInst.get(), idx,
221 this->cpu->readFloatRegBits(prev_phys_reg));
222 break;

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296
297 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
298 {
299 this->cpu->setCCReg(this->_destRegIdx[idx], val);
300 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
301 }
302
303#if THE_ISA == MIPS_ISA
214 case IntRegClass:
215 this->setIntRegOperand(this->staticInst.get(), idx,
216 this->cpu->readIntReg(prev_phys_reg));
217 break;
218 case FloatRegClass:
219 this->setFloatRegOperandBits(this->staticInst.get(), idx,
220 this->cpu->readFloatRegBits(prev_phys_reg));
221 break;

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295
296 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
297 {
298 this->cpu->setCCReg(this->_destRegIdx[idx], val);
299 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
300 }
301
302#if THE_ISA == MIPS_ISA
304 MiscReg readRegOtherThread(int misc_reg, ThreadID tid)
303 MiscReg readRegOtherThread(RegId misc_reg, ThreadID tid)
305 {
306 panic("MIPS MT not defined for O3 CPU.\n");
307 return 0;
308 }
309
304 {
305 panic("MIPS MT not defined for O3 CPU.\n");
306 return 0;
307 }
308
310 void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid)
309 void setRegOtherThread(RegId misc_reg, MiscReg val, ThreadID tid)
311 {
312 panic("MIPS MT not defined for O3 CPU.\n");
313 }
314#endif
315
316 public:
317 /** Calculates EA part of a memory instruction. Currently unused,
318 * though it may be useful in the future if we want to split

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311 panic("MIPS MT not defined for O3 CPU.\n");
312 }
313#endif
314
315 public:
316 /** Calculates EA part of a memory instruction. Currently unused,
317 * though it may be useful in the future if we want to split

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