dyn_inst.hh (10111:fd90d9e55e5c) dyn_inst.hh (10319:4207f9bfcceb)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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66 /** Extended machine instruction type. */
67 typedef TheISA::ExtMachInst ExtMachInst;
68 /** Logical register index type. */
69 typedef TheISA::RegIndex RegIndex;
70 /** Integer register index type. */
71 typedef TheISA::IntReg IntReg;
72 typedef TheISA::FloatReg FloatReg;
73 typedef TheISA::FloatRegBits FloatRegBits;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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66 /** Extended machine instruction type. */
67 typedef TheISA::ExtMachInst ExtMachInst;
68 /** Logical register index type. */
69 typedef TheISA::RegIndex RegIndex;
70 /** Integer register index type. */
71 typedef TheISA::IntReg IntReg;
72 typedef TheISA::FloatReg FloatReg;
73 typedef TheISA::FloatRegBits FloatRegBits;
74#ifdef ISA_HAS_CC_REGS
75 typedef TheISA::CCReg CCReg;
74 typedef TheISA::CCReg CCReg;
76#endif
75
77 /** Misc register index type. */
78 typedef TheISA::MiscReg MiscReg;
79
80 enum {
81 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
82 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
83 };
84

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245 // renaming. We find the architectural register index by indexing
246 // into the instruction's own operand index table. Note that a
247 // raw pointer to the StaticInst is provided instead of a
248 // ref-counted StaticInstPtr to redice overhead. This is fine as
249 // long as these methods don't copy the pointer into any long-term
250 // storage (which is pretty hard to imagine they would have reason
251 // to do).
252
76 /** Misc register index type. */
77 typedef TheISA::MiscReg MiscReg;
78
79 enum {
80 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
81 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
82 };
83

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244 // renaming. We find the architectural register index by indexing
245 // into the instruction's own operand index table. Note that a
246 // raw pointer to the StaticInst is provided instead of a
247 // ref-counted StaticInstPtr to redice overhead. This is fine as
248 // long as these methods don't copy the pointer into any long-term
249 // storage (which is pretty hard to imagine they would have reason
250 // to do).
251
253 uint64_t readIntRegOperand(const StaticInst *si, int idx)
252 IntReg readIntRegOperand(const StaticInst *si, int idx)
254 {
255 return this->cpu->readIntReg(this->_srcRegIdx[idx]);
256 }
257
258 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
259 {
260 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
261 }
262
263 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
264 {
265 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
266 }
267
253 {
254 return this->cpu->readIntReg(this->_srcRegIdx[idx]);
255 }
256
257 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
258 {
259 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
260 }
261
262 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
263 {
264 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
265 }
266
268 uint64_t readCCRegOperand(const StaticInst *si, int idx)
267 CCReg readCCRegOperand(const StaticInst *si, int idx)
269 {
270 return this->cpu->readCCReg(this->_srcRegIdx[idx]);
271 }
272
273 /** @todo: Make results into arrays so they can handle multiple dest
274 * registers.
275 */
268 {
269 return this->cpu->readCCReg(this->_srcRegIdx[idx]);
270 }
271
272 /** @todo: Make results into arrays so they can handle multiple dest
273 * registers.
274 */
276 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
275 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
277 {
278 this->cpu->setIntReg(this->_destRegIdx[idx], val);
279 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
280 }
281
282 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
283 {
284 this->cpu->setFloatReg(this->_destRegIdx[idx], val);
285 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
286 }
287
288 void setFloatRegOperandBits(const StaticInst *si, int idx,
289 FloatRegBits val)
290 {
291 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
292 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
293 }
294
276 {
277 this->cpu->setIntReg(this->_destRegIdx[idx], val);
278 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
279 }
280
281 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
282 {
283 this->cpu->setFloatReg(this->_destRegIdx[idx], val);
284 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
285 }
286
287 void setFloatRegOperandBits(const StaticInst *si, int idx,
288 FloatRegBits val)
289 {
290 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
291 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
292 }
293
295 void setCCRegOperand(const StaticInst *si, int idx, uint64_t val)
294 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
296 {
297 this->cpu->setCCReg(this->_destRegIdx[idx], val);
298 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
299 }
300
301#if THE_ISA == MIPS_ISA
295 {
296 this->cpu->setCCReg(this->_destRegIdx[idx], val);
297 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
298 }
299
300#if THE_ISA == MIPS_ISA
302 uint64_t readRegOtherThread(int misc_reg)
301 MiscReg readRegOtherThread(int misc_reg, ThreadID tid)
303 {
304 panic("MIPS MT not defined for O3 CPU.\n");
305 return 0;
306 }
307
302 {
303 panic("MIPS MT not defined for O3 CPU.\n");
304 return 0;
305 }
306
308 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
307 void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid)
309 {
310 panic("MIPS MT not defined for O3 CPU.\n");
311 }
312#endif
313
314 public:
315 /** Calculates EA part of a memory instruction. Currently unused,
316 * though it may be useful in the future if we want to split

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309 panic("MIPS MT not defined for O3 CPU.\n");
310 }
311#endif
312
313 public:
314 /** Calculates EA part of a memory instruction. Currently unused,
315 * though it may be useful in the future if we want to split

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