1/* 2 * Copyright (c) 2010 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 64 unchanged lines hidden (view full) --- 73 /** Extended machine instruction type. */ 74 typedef TheISA::ExtMachInst ExtMachInst; 75 /** Logical register index type. */ 76 typedef TheISA::RegIndex RegIndex; 77 /** Integer register index type. */ 78 typedef TheISA::IntReg IntReg; 79 typedef TheISA::FloatReg FloatReg; 80 typedef TheISA::FloatRegBits FloatRegBits; |
81#ifdef ISA_HAS_CC_REGS 82 typedef TheISA::CCReg CCReg; 83#endif |
84 /** Misc register index type. */ 85 typedef TheISA::MiscReg MiscReg; 86 87 enum { 88 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 89 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 90 }; 91 --- 128 unchanged lines hidden (view full) --- 220 case IntRegClass: 221 this->setIntRegOperand(this->staticInst.get(), idx, 222 this->cpu->readIntReg(prev_phys_reg)); 223 break; 224 case FloatRegClass: 225 this->setFloatRegOperandBits(this->staticInst.get(), idx, 226 this->cpu->readFloatRegBits(prev_phys_reg)); 227 break; |
228 case CCRegClass: 229 this->setCCRegOperand(this->staticInst.get(), idx, 230 this->cpu->readCCReg(prev_phys_reg)); 231 break; |
232 case MiscRegClass: 233 // no need to forward misc reg values 234 break; 235 } 236 } 237 } 238 /** Calls hardware return from error interrupt. */ 239 Fault hwrei(); --- 27 unchanged lines hidden (view full) --- 267 return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 268 } 269 270 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 271 { 272 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 273 } 274 |
275 uint64_t readCCRegOperand(const StaticInst *si, int idx) 276 { 277 return this->cpu->readCCReg(this->_srcRegIdx[idx]); 278 } 279 |
280 /** @todo: Make results into arrays so they can handle multiple dest 281 * registers. 282 */ 283 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 284 { 285 this->cpu->setIntReg(this->_destRegIdx[idx], val); 286 BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 287 } --- 6 unchanged lines hidden (view full) --- 294 295 void setFloatRegOperandBits(const StaticInst *si, int idx, 296 FloatRegBits val) 297 { 298 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 299 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 300 } 301 |
302 void setCCRegOperand(const StaticInst *si, int idx, uint64_t val) 303 { 304 this->cpu->setCCReg(this->_destRegIdx[idx], val); 305 BaseDynInst<Impl>::setCCRegOperand(si, idx, val); 306 } 307 |
308#if THE_ISA == MIPS_ISA 309 uint64_t readRegOtherThread(int misc_reg) 310 { 311 panic("MIPS MT not defined for O3 CPU.\n"); 312 return 0; 313 } 314 315 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val) --- 27 unchanged lines hidden --- |