1/* 2 * Copyright (c) 2010 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 57 unchanged lines hidden (view full) --- 66 /** Extended machine instruction type. */ 67 typedef TheISA::ExtMachInst ExtMachInst; 68 /** Logical register index type. */ 69 typedef TheISA::RegIndex RegIndex; 70 /** Integer register index type. */ 71 typedef TheISA::IntReg IntReg; 72 typedef TheISA::FloatReg FloatReg; 73 typedef TheISA::FloatRegBits FloatRegBits; |
74 typedef TheISA::CCReg CCReg; |
75 |
76 /** Misc register index type. */ 77 typedef TheISA::MiscReg MiscReg; 78 79 enum { 80 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 81 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 82 }; 83 --- 160 unchanged lines hidden (view full) --- 244 // renaming. We find the architectural register index by indexing 245 // into the instruction's own operand index table. Note that a 246 // raw pointer to the StaticInst is provided instead of a 247 // ref-counted StaticInstPtr to redice overhead. This is fine as 248 // long as these methods don't copy the pointer into any long-term 249 // storage (which is pretty hard to imagine they would have reason 250 // to do). 251 |
252 IntReg readIntRegOperand(const StaticInst *si, int idx) |
253 { 254 return this->cpu->readIntReg(this->_srcRegIdx[idx]); 255 } 256 257 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 258 { 259 return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 260 } 261 262 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 263 { 264 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 265 } 266 |
267 CCReg readCCRegOperand(const StaticInst *si, int idx) |
268 { 269 return this->cpu->readCCReg(this->_srcRegIdx[idx]); 270 } 271 272 /** @todo: Make results into arrays so they can handle multiple dest 273 * registers. 274 */ |
275 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) |
276 { 277 this->cpu->setIntReg(this->_destRegIdx[idx], val); 278 BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 279 } 280 281 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 282 { 283 this->cpu->setFloatReg(this->_destRegIdx[idx], val); 284 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); 285 } 286 287 void setFloatRegOperandBits(const StaticInst *si, int idx, 288 FloatRegBits val) 289 { 290 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 291 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 292 } 293 |
294 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) |
295 { 296 this->cpu->setCCReg(this->_destRegIdx[idx], val); 297 BaseDynInst<Impl>::setCCRegOperand(si, idx, val); 298 } 299 300#if THE_ISA == MIPS_ISA |
301 MiscReg readRegOtherThread(int misc_reg, ThreadID tid) |
302 { 303 panic("MIPS MT not defined for O3 CPU.\n"); 304 return 0; 305 } 306 |
307 void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) |
308 { 309 panic("MIPS MT not defined for O3 CPU.\n"); 310 } 311#endif 312 313 public: 314 /** Calculates EA part of a memory instruction. Currently unused, 315 * though it may be useful in the future if we want to split --- 19 unchanged lines hidden --- |