126c126
< Tick fetchTick; // instruction fetch is completed.
---
> Tick fetchTick; // instruction fetch is completed.
173,175c173,175
< RegId reg = si->srcRegIdx(idx);
< assert(reg.regClass == MiscRegClass);
< return this->cpu->readMiscReg(reg.regIdx, this->threadNumber);
---
> const RegId& reg = si->srcRegIdx(idx);
> assert(reg.isMiscReg());
> return this->cpu->readMiscReg(reg.index(), this->threadNumber);
184,186c184,186
< RegId reg = si->destRegIdx(idx);
< assert(reg.regClass == MiscRegClass);
< setMiscReg(reg.regIdx, val);
---
> const RegId& reg = si->destRegIdx(idx);
> assert(reg.isMiscReg());
> setMiscReg(reg.index(), val);
211c211
< RegId original_dest_reg =
---
> const RegId& original_dest_reg =
213c213
< switch (original_dest_reg.regClass) {
---
> switch (original_dest_reg.classValue()) {
303c303
< MiscReg readRegOtherThread(RegId misc_reg, ThreadID tid)
---
> MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid)
309c309
< void setRegOtherThread(RegId misc_reg, MiscReg val, ThreadID tid)
---
> void setRegOtherThread(const RegId& misc_reg, MiscReg val, ThreadID tid)