1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_DYN_INST_HH__
45#define __CPU_O3_DYN_INST_HH__
46
47#include "arch/isa_traits.hh"
48#include "config/the_isa.hh"
49#include "cpu/o3/cpu.hh"
50#include "cpu/o3/isa_specific.hh"
51#include "cpu/base_dyn_inst.hh"
52#include "cpu/inst_seq.hh"
53#include "cpu/reg_class.hh"
54
55class Packet;
56
57/**
58 * Mostly implementation & ISA specific AlphaDynInst. As with most
59 * other classes in the new CPU model, it is templated on the Impl to
60 * allow for passing in of all types, such as the CPU type and the ISA
61 * type. The AlphaDynInst serves as the primary interface to the CPU
62 * for instructions that are executing.
63 */
64template <class Impl>
65class BaseO3DynInst : public BaseDynInst<Impl>
66{
67 public:
68 /** Typedef for the CPU. */
69 typedef typename Impl::O3CPU O3CPU;
70
71 /** Binary machine instruction type. */
72 typedef TheISA::MachInst MachInst;
73 /** Extended machine instruction type. */
74 typedef TheISA::ExtMachInst ExtMachInst;
75 /** Logical register index type. */
76 typedef TheISA::RegIndex RegIndex;
77 /** Integer register index type. */
78 typedef TheISA::IntReg IntReg;
79 typedef TheISA::FloatReg FloatReg;
80 typedef TheISA::FloatRegBits FloatRegBits;
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_DYN_INST_HH__
45#define __CPU_O3_DYN_INST_HH__
46
47#include "arch/isa_traits.hh"
48#include "config/the_isa.hh"
49#include "cpu/o3/cpu.hh"
50#include "cpu/o3/isa_specific.hh"
51#include "cpu/base_dyn_inst.hh"
52#include "cpu/inst_seq.hh"
53#include "cpu/reg_class.hh"
54
55class Packet;
56
57/**
58 * Mostly implementation & ISA specific AlphaDynInst. As with most
59 * other classes in the new CPU model, it is templated on the Impl to
60 * allow for passing in of all types, such as the CPU type and the ISA
61 * type. The AlphaDynInst serves as the primary interface to the CPU
62 * for instructions that are executing.
63 */
64template <class Impl>
65class BaseO3DynInst : public BaseDynInst<Impl>
66{
67 public:
68 /** Typedef for the CPU. */
69 typedef typename Impl::O3CPU O3CPU;
70
71 /** Binary machine instruction type. */
72 typedef TheISA::MachInst MachInst;
73 /** Extended machine instruction type. */
74 typedef TheISA::ExtMachInst ExtMachInst;
75 /** Logical register index type. */
76 typedef TheISA::RegIndex RegIndex;
77 /** Integer register index type. */
78 typedef TheISA::IntReg IntReg;
79 typedef TheISA::FloatReg FloatReg;
80 typedef TheISA::FloatRegBits FloatRegBits;
|
| 81#ifdef ISA_HAS_CC_REGS
82 typedef TheISA::CCReg CCReg;
83#endif
|
81 /** Misc register index type. */
82 typedef TheISA::MiscReg MiscReg;
83
84 enum {
85 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
86 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
87 };
88
89 public:
90 /** BaseDynInst constructor given a binary instruction. */
91 BaseO3DynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
92 TheISA::PCState pc, TheISA::PCState predPC,
93 InstSeqNum seq_num, O3CPU *cpu);
94
95 /** BaseDynInst constructor given a static inst pointer. */
96 BaseO3DynInst(StaticInstPtr _staticInst, StaticInstPtr _macroop);
97
98 ~BaseO3DynInst();
99
100 /** Executes the instruction.*/
101 Fault execute();
102
103 /** Initiates the access. Only valid for memory operations. */
104 Fault initiateAcc();
105
106 /** Completes the access. Only valid for memory operations. */
107 Fault completeAcc(PacketPtr pkt);
108
109 private:
110 /** Initializes variables. */
111 void initVars();
112
113 protected:
114 /** Values to be written to the destination misc. registers. */
115 MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs];
116
117 /** Indexes of the destination misc. registers. They are needed to defer
118 * the write accesses to the misc. registers until the commit stage, when
119 * the instruction is out of its speculative state.
120 */
121 short _destMiscRegIdx[TheISA::MaxMiscDestRegs];
122
123 /** Number of destination misc. registers. */
124 uint8_t _numDestMiscRegs;
125
126
127 public:
128#if TRACING_ON
129 /** Tick records used for the pipeline activity viewer. */
130 Tick fetchTick; // instruction fetch is completed.
131 int32_t decodeTick; // instruction enters decode phase
132 int32_t renameTick; // instruction enters rename phase
133 int32_t dispatchTick;
134 int32_t issueTick;
135 int32_t completeTick;
136 int32_t commitTick;
137 int32_t storeTick;
138#endif
139
140 /** Reads a misc. register, including any side-effects the read
141 * might have as defined by the architecture.
142 */
143 MiscReg readMiscReg(int misc_reg)
144 {
145 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
146 }
147
148 /** Sets a misc. register, including any side-effects the write
149 * might have as defined by the architecture.
150 */
151 void setMiscReg(int misc_reg, const MiscReg &val)
152 {
153 /** Writes to misc. registers are recorded and deferred until the
154 * commit stage, when updateMiscRegs() is called. First, check if
155 * the misc reg has been written before and update its value to be
156 * committed instead of making a new entry. If not, make a new
157 * entry and record the write.
158 */
159 for (int idx = 0; idx < _numDestMiscRegs; idx++) {
160 if (_destMiscRegIdx[idx] == misc_reg) {
161 _destMiscRegVal[idx] = val;
162 return;
163 }
164 }
165
166 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
167 _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
168 _destMiscRegVal[_numDestMiscRegs] = val;
169 _numDestMiscRegs++;
170 }
171
172 /** Reads a misc. register, including any side-effects the read
173 * might have as defined by the architecture.
174 */
175 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
176 {
177 return this->cpu->readMiscReg(
178 si->srcRegIdx(idx) - TheISA::Misc_Reg_Base,
179 this->threadNumber);
180 }
181
182 /** Sets a misc. register, including any side-effects the write
183 * might have as defined by the architecture.
184 */
185 void setMiscRegOperand(const StaticInst *si, int idx,
186 const MiscReg &val)
187 {
188 int misc_reg = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
189 setMiscReg(misc_reg, val);
190 }
191
192 /** Called at the commit stage to update the misc. registers. */
193 void updateMiscRegs()
194 {
195 // @todo: Pretty convoluted way to avoid squashing from happening when
196 // using the TC during an instruction's execution (specifically for
197 // instructions that have side-effects that use the TC). Fix this.
198 // See cpu/o3/dyn_inst_impl.hh.
199 bool no_squash_from_TC = this->thread->noSquashFromTC;
200 this->thread->noSquashFromTC = true;
201
202 for (int i = 0; i < _numDestMiscRegs; i++)
203 this->cpu->setMiscReg(
204 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
205
206 this->thread->noSquashFromTC = no_squash_from_TC;
207 }
208
209 void forwardOldRegs()
210 {
211
212 for (int idx = 0; idx < this->numDestRegs(); idx++) {
213 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
214 TheISA::RegIndex original_dest_reg =
215 this->staticInst->destRegIdx(idx);
216 switch (regIdxToClass(original_dest_reg)) {
217 case IntRegClass:
218 this->setIntRegOperand(this->staticInst.get(), idx,
219 this->cpu->readIntReg(prev_phys_reg));
220 break;
221 case FloatRegClass:
222 this->setFloatRegOperandBits(this->staticInst.get(), idx,
223 this->cpu->readFloatRegBits(prev_phys_reg));
224 break;
| 84 /** Misc register index type. */
85 typedef TheISA::MiscReg MiscReg;
86
87 enum {
88 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
89 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
90 };
91
92 public:
93 /** BaseDynInst constructor given a binary instruction. */
94 BaseO3DynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
95 TheISA::PCState pc, TheISA::PCState predPC,
96 InstSeqNum seq_num, O3CPU *cpu);
97
98 /** BaseDynInst constructor given a static inst pointer. */
99 BaseO3DynInst(StaticInstPtr _staticInst, StaticInstPtr _macroop);
100
101 ~BaseO3DynInst();
102
103 /** Executes the instruction.*/
104 Fault execute();
105
106 /** Initiates the access. Only valid for memory operations. */
107 Fault initiateAcc();
108
109 /** Completes the access. Only valid for memory operations. */
110 Fault completeAcc(PacketPtr pkt);
111
112 private:
113 /** Initializes variables. */
114 void initVars();
115
116 protected:
117 /** Values to be written to the destination misc. registers. */
118 MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs];
119
120 /** Indexes of the destination misc. registers. They are needed to defer
121 * the write accesses to the misc. registers until the commit stage, when
122 * the instruction is out of its speculative state.
123 */
124 short _destMiscRegIdx[TheISA::MaxMiscDestRegs];
125
126 /** Number of destination misc. registers. */
127 uint8_t _numDestMiscRegs;
128
129
130 public:
131#if TRACING_ON
132 /** Tick records used for the pipeline activity viewer. */
133 Tick fetchTick; // instruction fetch is completed.
134 int32_t decodeTick; // instruction enters decode phase
135 int32_t renameTick; // instruction enters rename phase
136 int32_t dispatchTick;
137 int32_t issueTick;
138 int32_t completeTick;
139 int32_t commitTick;
140 int32_t storeTick;
141#endif
142
143 /** Reads a misc. register, including any side-effects the read
144 * might have as defined by the architecture.
145 */
146 MiscReg readMiscReg(int misc_reg)
147 {
148 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
149 }
150
151 /** Sets a misc. register, including any side-effects the write
152 * might have as defined by the architecture.
153 */
154 void setMiscReg(int misc_reg, const MiscReg &val)
155 {
156 /** Writes to misc. registers are recorded and deferred until the
157 * commit stage, when updateMiscRegs() is called. First, check if
158 * the misc reg has been written before and update its value to be
159 * committed instead of making a new entry. If not, make a new
160 * entry and record the write.
161 */
162 for (int idx = 0; idx < _numDestMiscRegs; idx++) {
163 if (_destMiscRegIdx[idx] == misc_reg) {
164 _destMiscRegVal[idx] = val;
165 return;
166 }
167 }
168
169 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
170 _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
171 _destMiscRegVal[_numDestMiscRegs] = val;
172 _numDestMiscRegs++;
173 }
174
175 /** Reads a misc. register, including any side-effects the read
176 * might have as defined by the architecture.
177 */
178 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
179 {
180 return this->cpu->readMiscReg(
181 si->srcRegIdx(idx) - TheISA::Misc_Reg_Base,
182 this->threadNumber);
183 }
184
185 /** Sets a misc. register, including any side-effects the write
186 * might have as defined by the architecture.
187 */
188 void setMiscRegOperand(const StaticInst *si, int idx,
189 const MiscReg &val)
190 {
191 int misc_reg = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
192 setMiscReg(misc_reg, val);
193 }
194
195 /** Called at the commit stage to update the misc. registers. */
196 void updateMiscRegs()
197 {
198 // @todo: Pretty convoluted way to avoid squashing from happening when
199 // using the TC during an instruction's execution (specifically for
200 // instructions that have side-effects that use the TC). Fix this.
201 // See cpu/o3/dyn_inst_impl.hh.
202 bool no_squash_from_TC = this->thread->noSquashFromTC;
203 this->thread->noSquashFromTC = true;
204
205 for (int i = 0; i < _numDestMiscRegs; i++)
206 this->cpu->setMiscReg(
207 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
208
209 this->thread->noSquashFromTC = no_squash_from_TC;
210 }
211
212 void forwardOldRegs()
213 {
214
215 for (int idx = 0; idx < this->numDestRegs(); idx++) {
216 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
217 TheISA::RegIndex original_dest_reg =
218 this->staticInst->destRegIdx(idx);
219 switch (regIdxToClass(original_dest_reg)) {
220 case IntRegClass:
221 this->setIntRegOperand(this->staticInst.get(), idx,
222 this->cpu->readIntReg(prev_phys_reg));
223 break;
224 case FloatRegClass:
225 this->setFloatRegOperandBits(this->staticInst.get(), idx,
226 this->cpu->readFloatRegBits(prev_phys_reg));
227 break;
|
| 228 case CCRegClass:
229 this->setCCRegOperand(this->staticInst.get(), idx,
230 this->cpu->readCCReg(prev_phys_reg));
231 break;
|
225 case MiscRegClass:
226 // no need to forward misc reg values
227 break;
228 }
229 }
230 }
231 /** Calls hardware return from error interrupt. */
232 Fault hwrei();
233 /** Traps to handle specified fault. */
234 void trap(Fault fault);
235 bool simPalCheck(int palFunc);
236
237 /** Emulates a syscall. */
238 void syscall(int64_t callnum);
239
240 public:
241
242 // The register accessor methods provide the index of the
243 // instruction's operand (e.g., 0 or 1), not the architectural
244 // register index, to simplify the implementation of register
245 // renaming. We find the architectural register index by indexing
246 // into the instruction's own operand index table. Note that a
247 // raw pointer to the StaticInst is provided instead of a
248 // ref-counted StaticInstPtr to redice overhead. This is fine as
249 // long as these methods don't copy the pointer into any long-term
250 // storage (which is pretty hard to imagine they would have reason
251 // to do).
252
253 uint64_t readIntRegOperand(const StaticInst *si, int idx)
254 {
255 return this->cpu->readIntReg(this->_srcRegIdx[idx]);
256 }
257
258 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
259 {
260 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
261 }
262
263 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
264 {
265 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
266 }
267
| 232 case MiscRegClass:
233 // no need to forward misc reg values
234 break;
235 }
236 }
237 }
238 /** Calls hardware return from error interrupt. */
239 Fault hwrei();
240 /** Traps to handle specified fault. */
241 void trap(Fault fault);
242 bool simPalCheck(int palFunc);
243
244 /** Emulates a syscall. */
245 void syscall(int64_t callnum);
246
247 public:
248
249 // The register accessor methods provide the index of the
250 // instruction's operand (e.g., 0 or 1), not the architectural
251 // register index, to simplify the implementation of register
252 // renaming. We find the architectural register index by indexing
253 // into the instruction's own operand index table. Note that a
254 // raw pointer to the StaticInst is provided instead of a
255 // ref-counted StaticInstPtr to redice overhead. This is fine as
256 // long as these methods don't copy the pointer into any long-term
257 // storage (which is pretty hard to imagine they would have reason
258 // to do).
259
260 uint64_t readIntRegOperand(const StaticInst *si, int idx)
261 {
262 return this->cpu->readIntReg(this->_srcRegIdx[idx]);
263 }
264
265 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
266 {
267 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
268 }
269
270 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
271 {
272 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
273 }
274
|
| 275 uint64_t readCCRegOperand(const StaticInst *si, int idx)
276 {
277 return this->cpu->readCCReg(this->_srcRegIdx[idx]);
278 }
279
|
268 /** @todo: Make results into arrays so they can handle multiple dest
269 * registers.
270 */
271 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
272 {
273 this->cpu->setIntReg(this->_destRegIdx[idx], val);
274 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
275 }
276
277 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
278 {
279 this->cpu->setFloatReg(this->_destRegIdx[idx], val);
280 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
281 }
282
283 void setFloatRegOperandBits(const StaticInst *si, int idx,
284 FloatRegBits val)
285 {
286 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
287 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
288 }
289
| 280 /** @todo: Make results into arrays so they can handle multiple dest
281 * registers.
282 */
283 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
284 {
285 this->cpu->setIntReg(this->_destRegIdx[idx], val);
286 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
287 }
288
289 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
290 {
291 this->cpu->setFloatReg(this->_destRegIdx[idx], val);
292 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
293 }
294
295 void setFloatRegOperandBits(const StaticInst *si, int idx,
296 FloatRegBits val)
297 {
298 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
299 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
300 }
301
|
| 302 void setCCRegOperand(const StaticInst *si, int idx, uint64_t val)
303 {
304 this->cpu->setCCReg(this->_destRegIdx[idx], val);
305 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
306 }
307
|
290#if THE_ISA == MIPS_ISA
291 uint64_t readRegOtherThread(int misc_reg)
292 {
293 panic("MIPS MT not defined for O3 CPU.\n");
294 return 0;
295 }
296
297 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
298 {
299 panic("MIPS MT not defined for O3 CPU.\n");
300 }
301#endif
302
303 public:
304 /** Calculates EA part of a memory instruction. Currently unused,
305 * though it may be useful in the future if we want to split
306 * memory operations into EA calculation and memory access parts.
307 */
308 Fault calcEA()
309 {
310 return this->staticInst->eaCompInst()->execute(this, this->traceData);
311 }
312
313 /** Does the memory access part of a memory instruction. Currently unused,
314 * though it may be useful in the future if we want to split
315 * memory operations into EA calculation and memory access parts.
316 */
317 Fault memAccess()
318 {
319 return this->staticInst->memAccInst()->execute(this, this->traceData);
320 }
321};
322
323#endif // __CPU_O3_ALPHA_DYN_INST_HH__
324
| 308#if THE_ISA == MIPS_ISA
309 uint64_t readRegOtherThread(int misc_reg)
310 {
311 panic("MIPS MT not defined for O3 CPU.\n");
312 return 0;
313 }
314
315 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
316 {
317 panic("MIPS MT not defined for O3 CPU.\n");
318 }
319#endif
320
321 public:
322 /** Calculates EA part of a memory instruction. Currently unused,
323 * though it may be useful in the future if we want to split
324 * memory operations into EA calculation and memory access parts.
325 */
326 Fault calcEA()
327 {
328 return this->staticInst->eaCompInst()->execute(this, this->traceData);
329 }
330
331 /** Does the memory access part of a memory instruction. Currently unused,
332 * though it may be useful in the future if we want to split
333 * memory operations into EA calculation and memory access parts.
334 */
335 Fault memAccess()
336 {
337 return this->staticInst->memAccInst()->execute(this, this->traceData);
338 }
339};
340
341#endif // __CPU_O3_ALPHA_DYN_INST_HH__
342
|