1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_DYN_INST_HH__
44#define __CPU_O3_DYN_INST_HH__
45
46#include "arch/isa_traits.hh"
47#include "config/the_isa.hh"
48#include "cpu/o3/cpu.hh"
49#include "cpu/o3/isa_specific.hh"
50#include "cpu/base_dyn_inst.hh"
51#include "cpu/inst_seq.hh"
52
53class Packet;
54
55/**
56 * Mostly implementation & ISA specific AlphaDynInst. As with most
57 * other classes in the new CPU model, it is templated on the Impl to
58 * allow for passing in of all types, such as the CPU type and the ISA
59 * type. The AlphaDynInst serves as the primary interface to the CPU
60 * for instructions that are executing.
61 */
62template <class Impl>
63class BaseO3DynInst : public BaseDynInst<Impl>
64{
65 public:
66 /** Typedef for the CPU. */
67 typedef typename Impl::O3CPU O3CPU;
68
69 /** Binary machine instruction type. */
70 typedef TheISA::MachInst MachInst;
71 /** Extended machine instruction type. */
72 typedef TheISA::ExtMachInst ExtMachInst;
73 /** Logical register index type. */
74 typedef TheISA::RegIndex RegIndex;
75 /** Integer register index type. */
76 typedef TheISA::IntReg IntReg;
77 typedef TheISA::FloatReg FloatReg;
78 typedef TheISA::FloatRegBits FloatRegBits;
79 /** Misc register index type. */
80 typedef TheISA::MiscReg MiscReg;
81
82 enum {
83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
84 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
85 };
86
87 public:
88 /** BaseDynInst constructor given a binary instruction. */
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_DYN_INST_HH__
44#define __CPU_O3_DYN_INST_HH__
45
46#include "arch/isa_traits.hh"
47#include "config/the_isa.hh"
48#include "cpu/o3/cpu.hh"
49#include "cpu/o3/isa_specific.hh"
50#include "cpu/base_dyn_inst.hh"
51#include "cpu/inst_seq.hh"
52
53class Packet;
54
55/**
56 * Mostly implementation & ISA specific AlphaDynInst. As with most
57 * other classes in the new CPU model, it is templated on the Impl to
58 * allow for passing in of all types, such as the CPU type and the ISA
59 * type. The AlphaDynInst serves as the primary interface to the CPU
60 * for instructions that are executing.
61 */
62template <class Impl>
63class BaseO3DynInst : public BaseDynInst<Impl>
64{
65 public:
66 /** Typedef for the CPU. */
67 typedef typename Impl::O3CPU O3CPU;
68
69 /** Binary machine instruction type. */
70 typedef TheISA::MachInst MachInst;
71 /** Extended machine instruction type. */
72 typedef TheISA::ExtMachInst ExtMachInst;
73 /** Logical register index type. */
74 typedef TheISA::RegIndex RegIndex;
75 /** Integer register index type. */
76 typedef TheISA::IntReg IntReg;
77 typedef TheISA::FloatReg FloatReg;
78 typedef TheISA::FloatRegBits FloatRegBits;
79 /** Misc register index type. */
80 typedef TheISA::MiscReg MiscReg;
81
82 enum {
83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
84 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
85 };
86
87 public:
88 /** BaseDynInst constructor given a binary instruction. */
|
95
96 /** Executes the instruction.*/
97 Fault execute();
98
99 /** Initiates the access. Only valid for memory operations. */
100 Fault initiateAcc();
101
102 /** Completes the access. Only valid for memory operations. */
103 Fault completeAcc(PacketPtr pkt);
104
105 private:
106 /** Initializes variables. */
107 void initVars();
108
109 protected:
110 /** Indexes of the destination misc. registers. They are needed to defer
111 * the write accesses to the misc. registers until the commit stage, when
112 * the instruction is out of its speculative state.
113 */
114 int _destMiscRegIdx[MaxInstDestRegs];
115 /** Values to be written to the destination misc. registers. */
116 MiscReg _destMiscRegVal[MaxInstDestRegs];
117 /** Number of destination misc. registers. */
118 int _numDestMiscRegs;
119
120 public:
121
122#if TRACING_ON
123 /** Tick records used for the pipeline activity viewer. */
124 Tick fetchTick;
125 Tick decodeTick;
126 Tick renameTick;
127 Tick dispatchTick;
128 Tick issueTick;
129 Tick completeTick;
130#endif
131
132 /** Reads a misc. register, including any side-effects the read
133 * might have as defined by the architecture.
134 */
135 MiscReg readMiscReg(int misc_reg)
136 {
137 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
138 }
139
140 /** Sets a misc. register, including any side-effects the write
141 * might have as defined by the architecture.
142 */
143 void setMiscReg(int misc_reg, const MiscReg &val)
144 {
145 /** Writes to misc. registers are recorded and deferred until the
146 * commit stage, when updateMiscRegs() is called.
147 */
148 _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
149 _destMiscRegVal[_numDestMiscRegs] = val;
150 _numDestMiscRegs++;
151 }
152
153 /** Reads a misc. register, including any side-effects the read
154 * might have as defined by the architecture.
155 */
156 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
157 {
158 return this->cpu->readMiscReg(
159 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
160 this->threadNumber);
161 }
162
163 /** Sets a misc. register, including any side-effects the write
164 * might have as defined by the architecture.
165 */
166 void setMiscRegOperand(const StaticInst *si, int idx,
167 const MiscReg &val)
168 {
169 int misc_reg = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
170 setMiscReg(misc_reg, val);
171 }
172
173 /** Called at the commit stage to update the misc. registers. */
174 void updateMiscRegs()
175 {
176 // @todo: Pretty convoluted way to avoid squashing from happening when
177 // using the TC during an instruction's execution (specifically for
178 // instructions that have side-effects that use the TC). Fix this.
179 // See cpu/o3/dyn_inst_impl.hh.
180 bool in_syscall = this->thread->inSyscall;
181 this->thread->inSyscall = true;
182
183 for (int i = 0; i < _numDestMiscRegs; i++)
184 this->cpu->setMiscReg(
185 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
186
187 this->thread->inSyscall = in_syscall;
188 }
189
190 void forwardOldRegs()
191 {
192
193 for (int idx = 0; idx < this->numDestRegs(); idx++) {
194 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
195 TheISA::RegIndex original_dest_reg = this->staticInst->destRegIdx(idx);
196 if (original_dest_reg < TheISA::FP_Base_DepTag)
197 this->setIntRegOperand(this->staticInst.get(), idx, this->cpu->readIntReg(prev_phys_reg));
198 else if (original_dest_reg < TheISA::Ctrl_Base_DepTag)
199 this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg));
200 }
201 }
202#if FULL_SYSTEM
203 /** Calls hardware return from error interrupt. */
204 Fault hwrei();
205 /** Traps to handle specified fault. */
206 void trap(Fault fault);
207 bool simPalCheck(int palFunc);
208#else
209 /** Calls a syscall. */
210 void syscall(int64_t callnum);
211#endif
212
213 public:
214
215 // The register accessor methods provide the index of the
216 // instruction's operand (e.g., 0 or 1), not the architectural
217 // register index, to simplify the implementation of register
218 // renaming. We find the architectural register index by indexing
219 // into the instruction's own operand index table. Note that a
220 // raw pointer to the StaticInst is provided instead of a
221 // ref-counted StaticInstPtr to redice overhead. This is fine as
222 // long as these methods don't copy the pointer into any long-term
223 // storage (which is pretty hard to imagine they would have reason
224 // to do).
225
226 uint64_t readIntRegOperand(const StaticInst *si, int idx)
227 {
228 return this->cpu->readIntReg(this->_srcRegIdx[idx]);
229 }
230
231 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
232 {
233 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
234 }
235
236 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
237 {
238 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
239 }
240
241 /** @todo: Make results into arrays so they can handle multiple dest
242 * registers.
243 */
244 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
245 {
246 this->cpu->setIntReg(this->_destRegIdx[idx], val);
247 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
248 }
249
250 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
251 {
252 this->cpu->setFloatReg(this->_destRegIdx[idx], val);
253 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
254 }
255
256 void setFloatRegOperandBits(const StaticInst *si, int idx,
257 FloatRegBits val)
258 {
259 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
260 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
261 }
262
263#if THE_ISA == MIPS_ISA
264 uint64_t readRegOtherThread(int misc_reg)
265 {
266 panic("MIPS MT not defined for O3 CPU.\n");
267 return 0;
268 }
269
270 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
271 {
272 panic("MIPS MT not defined for O3 CPU.\n");
273 }
274#endif
275
276 public:
277 /** Calculates EA part of a memory instruction. Currently unused,
278 * though it may be useful in the future if we want to split
279 * memory operations into EA calculation and memory access parts.
280 */
281 Fault calcEA()
282 {
283 return this->staticInst->eaCompInst()->execute(this, this->traceData);
284 }
285
286 /** Does the memory access part of a memory instruction. Currently unused,
287 * though it may be useful in the future if we want to split
288 * memory operations into EA calculation and memory access parts.
289 */
290 Fault memAccess()
291 {
292 return this->staticInst->memAccInst()->execute(this, this->traceData);
293 }
294};
295
296#endif // __CPU_O3_ALPHA_DYN_INST_HH__
297
| 95
96 /** Executes the instruction.*/
97 Fault execute();
98
99 /** Initiates the access. Only valid for memory operations. */
100 Fault initiateAcc();
101
102 /** Completes the access. Only valid for memory operations. */
103 Fault completeAcc(PacketPtr pkt);
104
105 private:
106 /** Initializes variables. */
107 void initVars();
108
109 protected:
110 /** Indexes of the destination misc. registers. They are needed to defer
111 * the write accesses to the misc. registers until the commit stage, when
112 * the instruction is out of its speculative state.
113 */
114 int _destMiscRegIdx[MaxInstDestRegs];
115 /** Values to be written to the destination misc. registers. */
116 MiscReg _destMiscRegVal[MaxInstDestRegs];
117 /** Number of destination misc. registers. */
118 int _numDestMiscRegs;
119
120 public:
121
122#if TRACING_ON
123 /** Tick records used for the pipeline activity viewer. */
124 Tick fetchTick;
125 Tick decodeTick;
126 Tick renameTick;
127 Tick dispatchTick;
128 Tick issueTick;
129 Tick completeTick;
130#endif
131
132 /** Reads a misc. register, including any side-effects the read
133 * might have as defined by the architecture.
134 */
135 MiscReg readMiscReg(int misc_reg)
136 {
137 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
138 }
139
140 /** Sets a misc. register, including any side-effects the write
141 * might have as defined by the architecture.
142 */
143 void setMiscReg(int misc_reg, const MiscReg &val)
144 {
145 /** Writes to misc. registers are recorded and deferred until the
146 * commit stage, when updateMiscRegs() is called.
147 */
148 _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
149 _destMiscRegVal[_numDestMiscRegs] = val;
150 _numDestMiscRegs++;
151 }
152
153 /** Reads a misc. register, including any side-effects the read
154 * might have as defined by the architecture.
155 */
156 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
157 {
158 return this->cpu->readMiscReg(
159 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
160 this->threadNumber);
161 }
162
163 /** Sets a misc. register, including any side-effects the write
164 * might have as defined by the architecture.
165 */
166 void setMiscRegOperand(const StaticInst *si, int idx,
167 const MiscReg &val)
168 {
169 int misc_reg = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
170 setMiscReg(misc_reg, val);
171 }
172
173 /** Called at the commit stage to update the misc. registers. */
174 void updateMiscRegs()
175 {
176 // @todo: Pretty convoluted way to avoid squashing from happening when
177 // using the TC during an instruction's execution (specifically for
178 // instructions that have side-effects that use the TC). Fix this.
179 // See cpu/o3/dyn_inst_impl.hh.
180 bool in_syscall = this->thread->inSyscall;
181 this->thread->inSyscall = true;
182
183 for (int i = 0; i < _numDestMiscRegs; i++)
184 this->cpu->setMiscReg(
185 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
186
187 this->thread->inSyscall = in_syscall;
188 }
189
190 void forwardOldRegs()
191 {
192
193 for (int idx = 0; idx < this->numDestRegs(); idx++) {
194 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
195 TheISA::RegIndex original_dest_reg = this->staticInst->destRegIdx(idx);
196 if (original_dest_reg < TheISA::FP_Base_DepTag)
197 this->setIntRegOperand(this->staticInst.get(), idx, this->cpu->readIntReg(prev_phys_reg));
198 else if (original_dest_reg < TheISA::Ctrl_Base_DepTag)
199 this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg));
200 }
201 }
202#if FULL_SYSTEM
203 /** Calls hardware return from error interrupt. */
204 Fault hwrei();
205 /** Traps to handle specified fault. */
206 void trap(Fault fault);
207 bool simPalCheck(int palFunc);
208#else
209 /** Calls a syscall. */
210 void syscall(int64_t callnum);
211#endif
212
213 public:
214
215 // The register accessor methods provide the index of the
216 // instruction's operand (e.g., 0 or 1), not the architectural
217 // register index, to simplify the implementation of register
218 // renaming. We find the architectural register index by indexing
219 // into the instruction's own operand index table. Note that a
220 // raw pointer to the StaticInst is provided instead of a
221 // ref-counted StaticInstPtr to redice overhead. This is fine as
222 // long as these methods don't copy the pointer into any long-term
223 // storage (which is pretty hard to imagine they would have reason
224 // to do).
225
226 uint64_t readIntRegOperand(const StaticInst *si, int idx)
227 {
228 return this->cpu->readIntReg(this->_srcRegIdx[idx]);
229 }
230
231 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
232 {
233 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
234 }
235
236 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
237 {
238 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
239 }
240
241 /** @todo: Make results into arrays so they can handle multiple dest
242 * registers.
243 */
244 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
245 {
246 this->cpu->setIntReg(this->_destRegIdx[idx], val);
247 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
248 }
249
250 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
251 {
252 this->cpu->setFloatReg(this->_destRegIdx[idx], val);
253 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
254 }
255
256 void setFloatRegOperandBits(const StaticInst *si, int idx,
257 FloatRegBits val)
258 {
259 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
260 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
261 }
262
263#if THE_ISA == MIPS_ISA
264 uint64_t readRegOtherThread(int misc_reg)
265 {
266 panic("MIPS MT not defined for O3 CPU.\n");
267 return 0;
268 }
269
270 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
271 {
272 panic("MIPS MT not defined for O3 CPU.\n");
273 }
274#endif
275
276 public:
277 /** Calculates EA part of a memory instruction. Currently unused,
278 * though it may be useful in the future if we want to split
279 * memory operations into EA calculation and memory access parts.
280 */
281 Fault calcEA()
282 {
283 return this->staticInst->eaCompInst()->execute(this, this->traceData);
284 }
285
286 /** Does the memory access part of a memory instruction. Currently unused,
287 * though it may be useful in the future if we want to split
288 * memory operations into EA calculation and memory access parts.
289 */
290 Fault memAccess()
291 {
292 return this->staticInst->memAccInst()->execute(this, this->traceData);
293 }
294};
295
296#endif // __CPU_O3_ALPHA_DYN_INST_HH__
297
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