dyn_inst.hh (13830:b5d6aa6c0e99) dyn_inst.hh (13900:d4bcfecd871e)
1/*
2 * Copyright (c) 2010, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_DYN_INST_HH__
45#define __CPU_O3_DYN_INST_HH__
46
47#include <array>
48
49#include "arch/isa_traits.hh"
50#include "config/the_isa.hh"
51#include "cpu/o3/cpu.hh"
52#include "cpu/o3/isa_specific.hh"
53#include "cpu/base_dyn_inst.hh"
54#include "cpu/inst_seq.hh"
55#include "cpu/reg_class.hh"
56
57class Packet;
58
59template <class Impl>
60class BaseO3DynInst : public BaseDynInst<Impl>
61{
62 public:
63 /** Typedef for the CPU. */
64 typedef typename Impl::O3CPU O3CPU;
65
66 /** Binary machine instruction type. */
67 typedef TheISA::MachInst MachInst;
68 /** Register types. */
69 using VecRegContainer = TheISA::VecRegContainer;
70 using VecElem = TheISA::VecElem;
71 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
72 using VecPredRegContainer = TheISA::VecPredRegContainer;
73
74 enum {
75 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
76 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
77 };
78
79 public:
80 /** BaseDynInst constructor given a binary instruction. */
81 BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr
82 &macroop, TheISA::PCState pc, TheISA::PCState predPC,
83 InstSeqNum seq_num, O3CPU *cpu);
84
85 /** BaseDynInst constructor given a static inst pointer. */
86 BaseO3DynInst(const StaticInstPtr &_staticInst,
87 const StaticInstPtr &_macroop);
88
89 ~BaseO3DynInst();
90
91 /** Executes the instruction.*/
92 Fault execute();
93
94 /** Initiates the access. Only valid for memory operations. */
95 Fault initiateAcc();
96
97 /** Completes the access. Only valid for memory operations. */
98 Fault completeAcc(PacketPtr pkt);
99
100 private:
101 /** Initializes variables. */
102 void initVars();
103
104 protected:
105 /** Explicitation of dependent names. */
106 using BaseDynInst<Impl>::cpu;
107 using BaseDynInst<Impl>::_srcRegIdx;
108 using BaseDynInst<Impl>::_destRegIdx;
109
110 /** Values to be written to the destination misc. registers. */
111 std::array<RegVal, TheISA::MaxMiscDestRegs> _destMiscRegVal;
112
113 /** Indexes of the destination misc. registers. They are needed to defer
114 * the write accesses to the misc. registers until the commit stage, when
115 * the instruction is out of its speculative state.
116 */
117 std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx;
118
119 /** Number of destination misc. registers. */
120 uint8_t _numDestMiscRegs;
121
122
123 public:
124#if TRACING_ON
125 /** Tick records used for the pipeline activity viewer. */
126 Tick fetchTick; // instruction fetch is completed.
127 int32_t decodeTick; // instruction enters decode phase
128 int32_t renameTick; // instruction enters rename phase
129 int32_t dispatchTick;
130 int32_t issueTick;
131 int32_t completeTick;
132 int32_t commitTick;
133 int32_t storeTick;
134#endif
135
136 /** Reads a misc. register, including any side-effects the read
137 * might have as defined by the architecture.
138 */
139 RegVal
140 readMiscReg(int misc_reg) override
141 {
142 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
143 }
144
145 /** Sets a misc. register, including any side-effects the write
146 * might have as defined by the architecture.
147 */
148 void
149 setMiscReg(int misc_reg, RegVal val) override
150 {
151 /** Writes to misc. registers are recorded and deferred until the
152 * commit stage, when updateMiscRegs() is called. First, check if
153 * the misc reg has been written before and update its value to be
154 * committed instead of making a new entry. If not, make a new
155 * entry and record the write.
156 */
157 for (int idx = 0; idx < _numDestMiscRegs; idx++) {
158 if (_destMiscRegIdx[idx] == misc_reg) {
159 _destMiscRegVal[idx] = val;
160 return;
161 }
162 }
163
164 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
165 _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
166 _destMiscRegVal[_numDestMiscRegs] = val;
167 _numDestMiscRegs++;
168 }
169
170 /** Reads a misc. register, including any side-effects the read
171 * might have as defined by the architecture.
172 */
173 RegVal
174 readMiscRegOperand(const StaticInst *si, int idx) override
175 {
176 const RegId& reg = si->srcRegIdx(idx);
177 assert(reg.isMiscReg());
178 return this->cpu->readMiscReg(reg.index(), this->threadNumber);
179 }
180
181 /** Sets a misc. register, including any side-effects the write
182 * might have as defined by the architecture.
183 */
184 void
185 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
186 {
187 const RegId& reg = si->destRegIdx(idx);
188 assert(reg.isMiscReg());
189 setMiscReg(reg.index(), val);
190 }
191
192 /** Called at the commit stage to update the misc. registers. */
193 void
194 updateMiscRegs()
195 {
196 // @todo: Pretty convoluted way to avoid squashing from happening when
197 // using the TC during an instruction's execution (specifically for
198 // instructions that have side-effects that use the TC). Fix this.
199 // See cpu/o3/dyn_inst_impl.hh.
200 bool no_squash_from_TC = this->thread->noSquashFromTC;
201 this->thread->noSquashFromTC = true;
202
203 for (int i = 0; i < _numDestMiscRegs; i++)
204 this->cpu->setMiscReg(
205 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
206
207 this->thread->noSquashFromTC = no_squash_from_TC;
208 }
209
210 void forwardOldRegs()
211 {
212
213 for (int idx = 0; idx < this->numDestRegs(); idx++) {
214 PhysRegIdPtr prev_phys_reg = this->prevDestRegIdx(idx);
215 const RegId& original_dest_reg =
216 this->staticInst->destRegIdx(idx);
217 switch (original_dest_reg.classValue()) {
218 case IntRegClass:
219 this->setIntRegOperand(this->staticInst.get(), idx,
220 this->cpu->readIntReg(prev_phys_reg));
221 break;
222 case FloatRegClass:
223 this->setFloatRegOperandBits(this->staticInst.get(), idx,
224 this->cpu->readFloatReg(prev_phys_reg));
225 break;
226 case VecRegClass:
227 this->setVecRegOperand(this->staticInst.get(), idx,
228 this->cpu->readVecReg(prev_phys_reg));
229 break;
230 case VecElemClass:
231 this->setVecElemOperand(this->staticInst.get(), idx,
232 this->cpu->readVecElem(prev_phys_reg));
233 break;
234 case VecPredRegClass:
235 this->setVecPredRegOperand(this->staticInst.get(), idx,
236 this->cpu->readVecPredReg(prev_phys_reg));
237 break;
238 case CCRegClass:
239 this->setCCRegOperand(this->staticInst.get(), idx,
240 this->cpu->readCCReg(prev_phys_reg));
241 break;
242 case MiscRegClass:
243 // no need to forward misc reg values
244 break;
245 default:
246 panic("Unknown register class: %d",
247 (int)original_dest_reg.classValue());
248 }
249 }
250 }
251 /** Calls hardware return from error interrupt. */
252 Fault hwrei() override;
253 /** Traps to handle specified fault. */
254 void trap(const Fault &fault);
255 bool simPalCheck(int palFunc) override;
256
257 /** Emulates a syscall. */
258 void syscall(int64_t callnum, Fault *fault) override;
259
260 public:
261
262 // The register accessor methods provide the index of the
263 // instruction's operand (e.g., 0 or 1), not the architectural
264 // register index, to simplify the implementation of register
265 // renaming. We find the architectural register index by indexing
266 // into the instruction's own operand index table. Note that a
267 // raw pointer to the StaticInst is provided instead of a
268 // ref-counted StaticInstPtr to redice overhead. This is fine as
269 // long as these methods don't copy the pointer into any long-term
270 // storage (which is pretty hard to imagine they would have reason
271 // to do).
272
273 RegVal
274 readIntRegOperand(const StaticInst *si, int idx) override
275 {
276 return this->cpu->readIntReg(this->_srcRegIdx[idx]);
277 }
278
279 RegVal
280 readFloatRegOperandBits(const StaticInst *si, int idx) override
281 {
282 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
283 }
284
285 const VecRegContainer&
286 readVecRegOperand(const StaticInst *si, int idx) const override
287 {
288 return this->cpu->readVecReg(this->_srcRegIdx[idx]);
289 }
290
291 /**
292 * Read destination vector register operand for modification.
293 */
294 VecRegContainer&
295 getWritableVecRegOperand(const StaticInst *si, int idx) override
296 {
297 return this->cpu->getWritableVecReg(this->_destRegIdx[idx]);
298 }
299
300 /** Vector Register Lane Interfaces. */
301 /** @{ */
302 /** Reads source vector 8bit operand. */
303 ConstVecLane8
304 readVec8BitLaneOperand(const StaticInst *si, int idx) const override
305 {
306 return cpu->template readVecLane<uint8_t>(_srcRegIdx[idx]);
307 }
308
309 /** Reads source vector 16bit operand. */
310 ConstVecLane16
311 readVec16BitLaneOperand(const StaticInst *si, int idx) const override
312 {
313 return cpu->template readVecLane<uint16_t>(_srcRegIdx[idx]);
314 }
315
316 /** Reads source vector 32bit operand. */
317 ConstVecLane32
318 readVec32BitLaneOperand(const StaticInst *si, int idx) const override
319 {
320 return cpu->template readVecLane<uint32_t>(_srcRegIdx[idx]);
321 }
322
323 /** Reads source vector 64bit operand. */
324 ConstVecLane64
325 readVec64BitLaneOperand(const StaticInst *si, int idx) const override
326 {
327 return cpu->template readVecLane<uint64_t>(_srcRegIdx[idx]);
328 }
329
330 /** Write a lane of the destination vector operand. */
331 template <typename LD>
332 void
333 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
334 {
335 return cpu->template setVecLane(_destRegIdx[idx], val);
336 }
337 virtual void
338 setVecLaneOperand(const StaticInst *si, int idx,
339 const LaneData<LaneSize::Byte>& val) override
340 {
341 return setVecLaneOperandT(si, idx, val);
342 }
343 virtual void
344 setVecLaneOperand(const StaticInst *si, int idx,
345 const LaneData<LaneSize::TwoByte>& val) override
346 {
347 return setVecLaneOperandT(si, idx, val);
348 }
349 virtual void
350 setVecLaneOperand(const StaticInst *si, int idx,
351 const LaneData<LaneSize::FourByte>& val) override
352 {
353 return setVecLaneOperandT(si, idx, val);
354 }
355 virtual void
356 setVecLaneOperand(const StaticInst *si, int idx,
357 const LaneData<LaneSize::EightByte>& val) override
358 {
359 return setVecLaneOperandT(si, idx, val);
360 }
361 /** @} */
362
363 VecElem readVecElemOperand(const StaticInst *si, int idx) const override
364 {
365 return this->cpu->readVecElem(this->_srcRegIdx[idx]);
366 }
367
368 const VecPredRegContainer&
369 readVecPredRegOperand(const StaticInst *si, int idx) const override
370 {
371 return this->cpu->readVecPredReg(this->_srcRegIdx[idx]);
372 }
373
374 VecPredRegContainer&
375 getWritableVecPredRegOperand(const StaticInst *si, int idx) override
376 {
377 return this->cpu->getWritableVecPredReg(this->_destRegIdx[idx]);
378 }
379
380 RegVal
381 readCCRegOperand(const StaticInst *si, int idx) override
382 {
383 return this->cpu->readCCReg(this->_srcRegIdx[idx]);
384 }
385
386 /** @todo: Make results into arrays so they can handle multiple dest
387 * registers.
388 */
389 void
390 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
391 {
392 this->cpu->setIntReg(this->_destRegIdx[idx], val);
393 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
394 }
395
396 void
397 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
398 {
399 this->cpu->setFloatReg(this->_destRegIdx[idx], val);
400 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
401 }
402
403 void
404 setVecRegOperand(const StaticInst *si, int idx,
405 const VecRegContainer& val) override
406 {
407 this->cpu->setVecReg(this->_destRegIdx[idx], val);
408 BaseDynInst<Impl>::setVecRegOperand(si, idx, val);
409 }
410
411 void setVecElemOperand(const StaticInst *si, int idx,
412 const VecElem val) override
413 {
414 int reg_idx = idx;
415 this->cpu->setVecElem(this->_destRegIdx[reg_idx], val);
416 BaseDynInst<Impl>::setVecElemOperand(si, idx, val);
417 }
418
419 void
420 setVecPredRegOperand(const StaticInst *si, int idx,
421 const VecPredRegContainer& val) override
422 {
423 this->cpu->setVecPredReg(this->_destRegIdx[idx], val);
424 BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val);
425 }
426
427 void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
428 {
429 this->cpu->setCCReg(this->_destRegIdx[idx], val);
430 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
431 }
1/*
2 * Copyright (c) 2010, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_DYN_INST_HH__
45#define __CPU_O3_DYN_INST_HH__
46
47#include <array>
48
49#include "arch/isa_traits.hh"
50#include "config/the_isa.hh"
51#include "cpu/o3/cpu.hh"
52#include "cpu/o3/isa_specific.hh"
53#include "cpu/base_dyn_inst.hh"
54#include "cpu/inst_seq.hh"
55#include "cpu/reg_class.hh"
56
57class Packet;
58
59template <class Impl>
60class BaseO3DynInst : public BaseDynInst<Impl>
61{
62 public:
63 /** Typedef for the CPU. */
64 typedef typename Impl::O3CPU O3CPU;
65
66 /** Binary machine instruction type. */
67 typedef TheISA::MachInst MachInst;
68 /** Register types. */
69 using VecRegContainer = TheISA::VecRegContainer;
70 using VecElem = TheISA::VecElem;
71 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
72 using VecPredRegContainer = TheISA::VecPredRegContainer;
73
74 enum {
75 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
76 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
77 };
78
79 public:
80 /** BaseDynInst constructor given a binary instruction. */
81 BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr
82 &macroop, TheISA::PCState pc, TheISA::PCState predPC,
83 InstSeqNum seq_num, O3CPU *cpu);
84
85 /** BaseDynInst constructor given a static inst pointer. */
86 BaseO3DynInst(const StaticInstPtr &_staticInst,
87 const StaticInstPtr &_macroop);
88
89 ~BaseO3DynInst();
90
91 /** Executes the instruction.*/
92 Fault execute();
93
94 /** Initiates the access. Only valid for memory operations. */
95 Fault initiateAcc();
96
97 /** Completes the access. Only valid for memory operations. */
98 Fault completeAcc(PacketPtr pkt);
99
100 private:
101 /** Initializes variables. */
102 void initVars();
103
104 protected:
105 /** Explicitation of dependent names. */
106 using BaseDynInst<Impl>::cpu;
107 using BaseDynInst<Impl>::_srcRegIdx;
108 using BaseDynInst<Impl>::_destRegIdx;
109
110 /** Values to be written to the destination misc. registers. */
111 std::array<RegVal, TheISA::MaxMiscDestRegs> _destMiscRegVal;
112
113 /** Indexes of the destination misc. registers. They are needed to defer
114 * the write accesses to the misc. registers until the commit stage, when
115 * the instruction is out of its speculative state.
116 */
117 std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx;
118
119 /** Number of destination misc. registers. */
120 uint8_t _numDestMiscRegs;
121
122
123 public:
124#if TRACING_ON
125 /** Tick records used for the pipeline activity viewer. */
126 Tick fetchTick; // instruction fetch is completed.
127 int32_t decodeTick; // instruction enters decode phase
128 int32_t renameTick; // instruction enters rename phase
129 int32_t dispatchTick;
130 int32_t issueTick;
131 int32_t completeTick;
132 int32_t commitTick;
133 int32_t storeTick;
134#endif
135
136 /** Reads a misc. register, including any side-effects the read
137 * might have as defined by the architecture.
138 */
139 RegVal
140 readMiscReg(int misc_reg) override
141 {
142 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
143 }
144
145 /** Sets a misc. register, including any side-effects the write
146 * might have as defined by the architecture.
147 */
148 void
149 setMiscReg(int misc_reg, RegVal val) override
150 {
151 /** Writes to misc. registers are recorded and deferred until the
152 * commit stage, when updateMiscRegs() is called. First, check if
153 * the misc reg has been written before and update its value to be
154 * committed instead of making a new entry. If not, make a new
155 * entry and record the write.
156 */
157 for (int idx = 0; idx < _numDestMiscRegs; idx++) {
158 if (_destMiscRegIdx[idx] == misc_reg) {
159 _destMiscRegVal[idx] = val;
160 return;
161 }
162 }
163
164 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
165 _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
166 _destMiscRegVal[_numDestMiscRegs] = val;
167 _numDestMiscRegs++;
168 }
169
170 /** Reads a misc. register, including any side-effects the read
171 * might have as defined by the architecture.
172 */
173 RegVal
174 readMiscRegOperand(const StaticInst *si, int idx) override
175 {
176 const RegId& reg = si->srcRegIdx(idx);
177 assert(reg.isMiscReg());
178 return this->cpu->readMiscReg(reg.index(), this->threadNumber);
179 }
180
181 /** Sets a misc. register, including any side-effects the write
182 * might have as defined by the architecture.
183 */
184 void
185 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
186 {
187 const RegId& reg = si->destRegIdx(idx);
188 assert(reg.isMiscReg());
189 setMiscReg(reg.index(), val);
190 }
191
192 /** Called at the commit stage to update the misc. registers. */
193 void
194 updateMiscRegs()
195 {
196 // @todo: Pretty convoluted way to avoid squashing from happening when
197 // using the TC during an instruction's execution (specifically for
198 // instructions that have side-effects that use the TC). Fix this.
199 // See cpu/o3/dyn_inst_impl.hh.
200 bool no_squash_from_TC = this->thread->noSquashFromTC;
201 this->thread->noSquashFromTC = true;
202
203 for (int i = 0; i < _numDestMiscRegs; i++)
204 this->cpu->setMiscReg(
205 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
206
207 this->thread->noSquashFromTC = no_squash_from_TC;
208 }
209
210 void forwardOldRegs()
211 {
212
213 for (int idx = 0; idx < this->numDestRegs(); idx++) {
214 PhysRegIdPtr prev_phys_reg = this->prevDestRegIdx(idx);
215 const RegId& original_dest_reg =
216 this->staticInst->destRegIdx(idx);
217 switch (original_dest_reg.classValue()) {
218 case IntRegClass:
219 this->setIntRegOperand(this->staticInst.get(), idx,
220 this->cpu->readIntReg(prev_phys_reg));
221 break;
222 case FloatRegClass:
223 this->setFloatRegOperandBits(this->staticInst.get(), idx,
224 this->cpu->readFloatReg(prev_phys_reg));
225 break;
226 case VecRegClass:
227 this->setVecRegOperand(this->staticInst.get(), idx,
228 this->cpu->readVecReg(prev_phys_reg));
229 break;
230 case VecElemClass:
231 this->setVecElemOperand(this->staticInst.get(), idx,
232 this->cpu->readVecElem(prev_phys_reg));
233 break;
234 case VecPredRegClass:
235 this->setVecPredRegOperand(this->staticInst.get(), idx,
236 this->cpu->readVecPredReg(prev_phys_reg));
237 break;
238 case CCRegClass:
239 this->setCCRegOperand(this->staticInst.get(), idx,
240 this->cpu->readCCReg(prev_phys_reg));
241 break;
242 case MiscRegClass:
243 // no need to forward misc reg values
244 break;
245 default:
246 panic("Unknown register class: %d",
247 (int)original_dest_reg.classValue());
248 }
249 }
250 }
251 /** Calls hardware return from error interrupt. */
252 Fault hwrei() override;
253 /** Traps to handle specified fault. */
254 void trap(const Fault &fault);
255 bool simPalCheck(int palFunc) override;
256
257 /** Emulates a syscall. */
258 void syscall(int64_t callnum, Fault *fault) override;
259
260 public:
261
262 // The register accessor methods provide the index of the
263 // instruction's operand (e.g., 0 or 1), not the architectural
264 // register index, to simplify the implementation of register
265 // renaming. We find the architectural register index by indexing
266 // into the instruction's own operand index table. Note that a
267 // raw pointer to the StaticInst is provided instead of a
268 // ref-counted StaticInstPtr to redice overhead. This is fine as
269 // long as these methods don't copy the pointer into any long-term
270 // storage (which is pretty hard to imagine they would have reason
271 // to do).
272
273 RegVal
274 readIntRegOperand(const StaticInst *si, int idx) override
275 {
276 return this->cpu->readIntReg(this->_srcRegIdx[idx]);
277 }
278
279 RegVal
280 readFloatRegOperandBits(const StaticInst *si, int idx) override
281 {
282 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
283 }
284
285 const VecRegContainer&
286 readVecRegOperand(const StaticInst *si, int idx) const override
287 {
288 return this->cpu->readVecReg(this->_srcRegIdx[idx]);
289 }
290
291 /**
292 * Read destination vector register operand for modification.
293 */
294 VecRegContainer&
295 getWritableVecRegOperand(const StaticInst *si, int idx) override
296 {
297 return this->cpu->getWritableVecReg(this->_destRegIdx[idx]);
298 }
299
300 /** Vector Register Lane Interfaces. */
301 /** @{ */
302 /** Reads source vector 8bit operand. */
303 ConstVecLane8
304 readVec8BitLaneOperand(const StaticInst *si, int idx) const override
305 {
306 return cpu->template readVecLane<uint8_t>(_srcRegIdx[idx]);
307 }
308
309 /** Reads source vector 16bit operand. */
310 ConstVecLane16
311 readVec16BitLaneOperand(const StaticInst *si, int idx) const override
312 {
313 return cpu->template readVecLane<uint16_t>(_srcRegIdx[idx]);
314 }
315
316 /** Reads source vector 32bit operand. */
317 ConstVecLane32
318 readVec32BitLaneOperand(const StaticInst *si, int idx) const override
319 {
320 return cpu->template readVecLane<uint32_t>(_srcRegIdx[idx]);
321 }
322
323 /** Reads source vector 64bit operand. */
324 ConstVecLane64
325 readVec64BitLaneOperand(const StaticInst *si, int idx) const override
326 {
327 return cpu->template readVecLane<uint64_t>(_srcRegIdx[idx]);
328 }
329
330 /** Write a lane of the destination vector operand. */
331 template <typename LD>
332 void
333 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
334 {
335 return cpu->template setVecLane(_destRegIdx[idx], val);
336 }
337 virtual void
338 setVecLaneOperand(const StaticInst *si, int idx,
339 const LaneData<LaneSize::Byte>& val) override
340 {
341 return setVecLaneOperandT(si, idx, val);
342 }
343 virtual void
344 setVecLaneOperand(const StaticInst *si, int idx,
345 const LaneData<LaneSize::TwoByte>& val) override
346 {
347 return setVecLaneOperandT(si, idx, val);
348 }
349 virtual void
350 setVecLaneOperand(const StaticInst *si, int idx,
351 const LaneData<LaneSize::FourByte>& val) override
352 {
353 return setVecLaneOperandT(si, idx, val);
354 }
355 virtual void
356 setVecLaneOperand(const StaticInst *si, int idx,
357 const LaneData<LaneSize::EightByte>& val) override
358 {
359 return setVecLaneOperandT(si, idx, val);
360 }
361 /** @} */
362
363 VecElem readVecElemOperand(const StaticInst *si, int idx) const override
364 {
365 return this->cpu->readVecElem(this->_srcRegIdx[idx]);
366 }
367
368 const VecPredRegContainer&
369 readVecPredRegOperand(const StaticInst *si, int idx) const override
370 {
371 return this->cpu->readVecPredReg(this->_srcRegIdx[idx]);
372 }
373
374 VecPredRegContainer&
375 getWritableVecPredRegOperand(const StaticInst *si, int idx) override
376 {
377 return this->cpu->getWritableVecPredReg(this->_destRegIdx[idx]);
378 }
379
380 RegVal
381 readCCRegOperand(const StaticInst *si, int idx) override
382 {
383 return this->cpu->readCCReg(this->_srcRegIdx[idx]);
384 }
385
386 /** @todo: Make results into arrays so they can handle multiple dest
387 * registers.
388 */
389 void
390 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
391 {
392 this->cpu->setIntReg(this->_destRegIdx[idx], val);
393 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
394 }
395
396 void
397 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
398 {
399 this->cpu->setFloatReg(this->_destRegIdx[idx], val);
400 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
401 }
402
403 void
404 setVecRegOperand(const StaticInst *si, int idx,
405 const VecRegContainer& val) override
406 {
407 this->cpu->setVecReg(this->_destRegIdx[idx], val);
408 BaseDynInst<Impl>::setVecRegOperand(si, idx, val);
409 }
410
411 void setVecElemOperand(const StaticInst *si, int idx,
412 const VecElem val) override
413 {
414 int reg_idx = idx;
415 this->cpu->setVecElem(this->_destRegIdx[reg_idx], val);
416 BaseDynInst<Impl>::setVecElemOperand(si, idx, val);
417 }
418
419 void
420 setVecPredRegOperand(const StaticInst *si, int idx,
421 const VecPredRegContainer& val) override
422 {
423 this->cpu->setVecPredReg(this->_destRegIdx[idx], val);
424 BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val);
425 }
426
427 void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
428 {
429 this->cpu->setCCReg(this->_destRegIdx[idx], val);
430 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
431 }
432
433#if THE_ISA == MIPS_ISA
434 RegVal
435 readRegOtherThread(const RegId& misc_reg, ThreadID tid) override
436 {
437 panic("MIPS MT not defined for O3 CPU.\n");
438 return 0;
439 }
440
441 void
442 setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) override
443 {
444 panic("MIPS MT not defined for O3 CPU.\n");
445 }
446#endif
447};
448
449#endif // __CPU_O3_ALPHA_DYN_INST_HH__
450
432};
433
434#endif // __CPU_O3_ALPHA_DYN_INST_HH__
435