1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_DYN_INST_HH__
45#define __CPU_O3_DYN_INST_HH__
46
47#include "arch/isa_traits.hh"
48#include "config/the_isa.hh"
49#include "cpu/o3/cpu.hh"
50#include "cpu/o3/isa_specific.hh"
51#include "cpu/base_dyn_inst.hh"
52#include "cpu/inst_seq.hh"
53#include "cpu/reg_class.hh"
54
55class Packet;
56
57template <class Impl>
58class BaseO3DynInst : public BaseDynInst<Impl>
59{
60 public:
61 /** Typedef for the CPU. */
62 typedef typename Impl::O3CPU O3CPU;
63
64 /** Binary machine instruction type. */
65 typedef TheISA::MachInst MachInst;
66 /** Extended machine instruction type. */
67 typedef TheISA::ExtMachInst ExtMachInst;
68 /** Logical register index type. */
69 typedef TheISA::RegIndex RegIndex;
70 /** Integer register index type. */
71 typedef TheISA::IntReg IntReg;
72 typedef TheISA::FloatReg FloatReg;
73 typedef TheISA::FloatRegBits FloatRegBits;
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_DYN_INST_HH__
45#define __CPU_O3_DYN_INST_HH__
46
47#include "arch/isa_traits.hh"
48#include "config/the_isa.hh"
49#include "cpu/o3/cpu.hh"
50#include "cpu/o3/isa_specific.hh"
51#include "cpu/base_dyn_inst.hh"
52#include "cpu/inst_seq.hh"
53#include "cpu/reg_class.hh"
54
55class Packet;
56
57template <class Impl>
58class BaseO3DynInst : public BaseDynInst<Impl>
59{
60 public:
61 /** Typedef for the CPU. */
62 typedef typename Impl::O3CPU O3CPU;
63
64 /** Binary machine instruction type. */
65 typedef TheISA::MachInst MachInst;
66 /** Extended machine instruction type. */
67 typedef TheISA::ExtMachInst ExtMachInst;
68 /** Logical register index type. */
69 typedef TheISA::RegIndex RegIndex;
70 /** Integer register index type. */
71 typedef TheISA::IntReg IntReg;
72 typedef TheISA::FloatReg FloatReg;
73 typedef TheISA::FloatRegBits FloatRegBits;
|
74#ifdef ISA_HAS_CC_REGS
| |
75 typedef TheISA::CCReg CCReg;
| 74 typedef TheISA::CCReg CCReg;
|
76#endif
| 75
|
77 /** Misc register index type. */
78 typedef TheISA::MiscReg MiscReg;
79
80 enum {
81 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
82 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
83 };
84
85 public:
86 /** BaseDynInst constructor given a binary instruction. */
87 BaseO3DynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
88 TheISA::PCState pc, TheISA::PCState predPC,
89 InstSeqNum seq_num, O3CPU *cpu);
90
91 /** BaseDynInst constructor given a static inst pointer. */
92 BaseO3DynInst(StaticInstPtr _staticInst, StaticInstPtr _macroop);
93
94 ~BaseO3DynInst();
95
96 /** Executes the instruction.*/
97 Fault execute();
98
99 /** Initiates the access. Only valid for memory operations. */
100 Fault initiateAcc();
101
102 /** Completes the access. Only valid for memory operations. */
103 Fault completeAcc(PacketPtr pkt);
104
105 private:
106 /** Initializes variables. */
107 void initVars();
108
109 protected:
110 /** Values to be written to the destination misc. registers. */
111 MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs];
112
113 /** Indexes of the destination misc. registers. They are needed to defer
114 * the write accesses to the misc. registers until the commit stage, when
115 * the instruction is out of its speculative state.
116 */
117 short _destMiscRegIdx[TheISA::MaxMiscDestRegs];
118
119 /** Number of destination misc. registers. */
120 uint8_t _numDestMiscRegs;
121
122
123 public:
124#if TRACING_ON
125 /** Tick records used for the pipeline activity viewer. */
126 Tick fetchTick; // instruction fetch is completed.
127 int32_t decodeTick; // instruction enters decode phase
128 int32_t renameTick; // instruction enters rename phase
129 int32_t dispatchTick;
130 int32_t issueTick;
131 int32_t completeTick;
132 int32_t commitTick;
133 int32_t storeTick;
134#endif
135
136 /** Reads a misc. register, including any side-effects the read
137 * might have as defined by the architecture.
138 */
139 MiscReg readMiscReg(int misc_reg)
140 {
141 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
142 }
143
144 /** Sets a misc. register, including any side-effects the write
145 * might have as defined by the architecture.
146 */
147 void setMiscReg(int misc_reg, const MiscReg &val)
148 {
149 /** Writes to misc. registers are recorded and deferred until the
150 * commit stage, when updateMiscRegs() is called. First, check if
151 * the misc reg has been written before and update its value to be
152 * committed instead of making a new entry. If not, make a new
153 * entry and record the write.
154 */
155 for (int idx = 0; idx < _numDestMiscRegs; idx++) {
156 if (_destMiscRegIdx[idx] == misc_reg) {
157 _destMiscRegVal[idx] = val;
158 return;
159 }
160 }
161
162 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
163 _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
164 _destMiscRegVal[_numDestMiscRegs] = val;
165 _numDestMiscRegs++;
166 }
167
168 /** Reads a misc. register, including any side-effects the read
169 * might have as defined by the architecture.
170 */
171 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
172 {
173 return this->cpu->readMiscReg(
174 si->srcRegIdx(idx) - TheISA::Misc_Reg_Base,
175 this->threadNumber);
176 }
177
178 /** Sets a misc. register, including any side-effects the write
179 * might have as defined by the architecture.
180 */
181 void setMiscRegOperand(const StaticInst *si, int idx,
182 const MiscReg &val)
183 {
184 int misc_reg = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
185 setMiscReg(misc_reg, val);
186 }
187
188 /** Called at the commit stage to update the misc. registers. */
189 void updateMiscRegs()
190 {
191 // @todo: Pretty convoluted way to avoid squashing from happening when
192 // using the TC during an instruction's execution (specifically for
193 // instructions that have side-effects that use the TC). Fix this.
194 // See cpu/o3/dyn_inst_impl.hh.
195 bool no_squash_from_TC = this->thread->noSquashFromTC;
196 this->thread->noSquashFromTC = true;
197
198 for (int i = 0; i < _numDestMiscRegs; i++)
199 this->cpu->setMiscReg(
200 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
201
202 this->thread->noSquashFromTC = no_squash_from_TC;
203 }
204
205 void forwardOldRegs()
206 {
207
208 for (int idx = 0; idx < this->numDestRegs(); idx++) {
209 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
210 TheISA::RegIndex original_dest_reg =
211 this->staticInst->destRegIdx(idx);
212 switch (regIdxToClass(original_dest_reg)) {
213 case IntRegClass:
214 this->setIntRegOperand(this->staticInst.get(), idx,
215 this->cpu->readIntReg(prev_phys_reg));
216 break;
217 case FloatRegClass:
218 this->setFloatRegOperandBits(this->staticInst.get(), idx,
219 this->cpu->readFloatRegBits(prev_phys_reg));
220 break;
221 case CCRegClass:
222 this->setCCRegOperand(this->staticInst.get(), idx,
223 this->cpu->readCCReg(prev_phys_reg));
224 break;
225 case MiscRegClass:
226 // no need to forward misc reg values
227 break;
228 }
229 }
230 }
231 /** Calls hardware return from error interrupt. */
232 Fault hwrei();
233 /** Traps to handle specified fault. */
234 void trap(Fault fault);
235 bool simPalCheck(int palFunc);
236
237 /** Emulates a syscall. */
238 void syscall(int64_t callnum);
239
240 public:
241
242 // The register accessor methods provide the index of the
243 // instruction's operand (e.g., 0 or 1), not the architectural
244 // register index, to simplify the implementation of register
245 // renaming. We find the architectural register index by indexing
246 // into the instruction's own operand index table. Note that a
247 // raw pointer to the StaticInst is provided instead of a
248 // ref-counted StaticInstPtr to redice overhead. This is fine as
249 // long as these methods don't copy the pointer into any long-term
250 // storage (which is pretty hard to imagine they would have reason
251 // to do).
252
| 76 /** Misc register index type. */
77 typedef TheISA::MiscReg MiscReg;
78
79 enum {
80 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
81 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
82 };
83
84 public:
85 /** BaseDynInst constructor given a binary instruction. */
86 BaseO3DynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
87 TheISA::PCState pc, TheISA::PCState predPC,
88 InstSeqNum seq_num, O3CPU *cpu);
89
90 /** BaseDynInst constructor given a static inst pointer. */
91 BaseO3DynInst(StaticInstPtr _staticInst, StaticInstPtr _macroop);
92
93 ~BaseO3DynInst();
94
95 /** Executes the instruction.*/
96 Fault execute();
97
98 /** Initiates the access. Only valid for memory operations. */
99 Fault initiateAcc();
100
101 /** Completes the access. Only valid for memory operations. */
102 Fault completeAcc(PacketPtr pkt);
103
104 private:
105 /** Initializes variables. */
106 void initVars();
107
108 protected:
109 /** Values to be written to the destination misc. registers. */
110 MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs];
111
112 /** Indexes of the destination misc. registers. They are needed to defer
113 * the write accesses to the misc. registers until the commit stage, when
114 * the instruction is out of its speculative state.
115 */
116 short _destMiscRegIdx[TheISA::MaxMiscDestRegs];
117
118 /** Number of destination misc. registers. */
119 uint8_t _numDestMiscRegs;
120
121
122 public:
123#if TRACING_ON
124 /** Tick records used for the pipeline activity viewer. */
125 Tick fetchTick; // instruction fetch is completed.
126 int32_t decodeTick; // instruction enters decode phase
127 int32_t renameTick; // instruction enters rename phase
128 int32_t dispatchTick;
129 int32_t issueTick;
130 int32_t completeTick;
131 int32_t commitTick;
132 int32_t storeTick;
133#endif
134
135 /** Reads a misc. register, including any side-effects the read
136 * might have as defined by the architecture.
137 */
138 MiscReg readMiscReg(int misc_reg)
139 {
140 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
141 }
142
143 /** Sets a misc. register, including any side-effects the write
144 * might have as defined by the architecture.
145 */
146 void setMiscReg(int misc_reg, const MiscReg &val)
147 {
148 /** Writes to misc. registers are recorded and deferred until the
149 * commit stage, when updateMiscRegs() is called. First, check if
150 * the misc reg has been written before and update its value to be
151 * committed instead of making a new entry. If not, make a new
152 * entry and record the write.
153 */
154 for (int idx = 0; idx < _numDestMiscRegs; idx++) {
155 if (_destMiscRegIdx[idx] == misc_reg) {
156 _destMiscRegVal[idx] = val;
157 return;
158 }
159 }
160
161 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
162 _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
163 _destMiscRegVal[_numDestMiscRegs] = val;
164 _numDestMiscRegs++;
165 }
166
167 /** Reads a misc. register, including any side-effects the read
168 * might have as defined by the architecture.
169 */
170 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
171 {
172 return this->cpu->readMiscReg(
173 si->srcRegIdx(idx) - TheISA::Misc_Reg_Base,
174 this->threadNumber);
175 }
176
177 /** Sets a misc. register, including any side-effects the write
178 * might have as defined by the architecture.
179 */
180 void setMiscRegOperand(const StaticInst *si, int idx,
181 const MiscReg &val)
182 {
183 int misc_reg = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
184 setMiscReg(misc_reg, val);
185 }
186
187 /** Called at the commit stage to update the misc. registers. */
188 void updateMiscRegs()
189 {
190 // @todo: Pretty convoluted way to avoid squashing from happening when
191 // using the TC during an instruction's execution (specifically for
192 // instructions that have side-effects that use the TC). Fix this.
193 // See cpu/o3/dyn_inst_impl.hh.
194 bool no_squash_from_TC = this->thread->noSquashFromTC;
195 this->thread->noSquashFromTC = true;
196
197 for (int i = 0; i < _numDestMiscRegs; i++)
198 this->cpu->setMiscReg(
199 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
200
201 this->thread->noSquashFromTC = no_squash_from_TC;
202 }
203
204 void forwardOldRegs()
205 {
206
207 for (int idx = 0; idx < this->numDestRegs(); idx++) {
208 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
209 TheISA::RegIndex original_dest_reg =
210 this->staticInst->destRegIdx(idx);
211 switch (regIdxToClass(original_dest_reg)) {
212 case IntRegClass:
213 this->setIntRegOperand(this->staticInst.get(), idx,
214 this->cpu->readIntReg(prev_phys_reg));
215 break;
216 case FloatRegClass:
217 this->setFloatRegOperandBits(this->staticInst.get(), idx,
218 this->cpu->readFloatRegBits(prev_phys_reg));
219 break;
220 case CCRegClass:
221 this->setCCRegOperand(this->staticInst.get(), idx,
222 this->cpu->readCCReg(prev_phys_reg));
223 break;
224 case MiscRegClass:
225 // no need to forward misc reg values
226 break;
227 }
228 }
229 }
230 /** Calls hardware return from error interrupt. */
231 Fault hwrei();
232 /** Traps to handle specified fault. */
233 void trap(Fault fault);
234 bool simPalCheck(int palFunc);
235
236 /** Emulates a syscall. */
237 void syscall(int64_t callnum);
238
239 public:
240
241 // The register accessor methods provide the index of the
242 // instruction's operand (e.g., 0 or 1), not the architectural
243 // register index, to simplify the implementation of register
244 // renaming. We find the architectural register index by indexing
245 // into the instruction's own operand index table. Note that a
246 // raw pointer to the StaticInst is provided instead of a
247 // ref-counted StaticInstPtr to redice overhead. This is fine as
248 // long as these methods don't copy the pointer into any long-term
249 // storage (which is pretty hard to imagine they would have reason
250 // to do).
251
|
253 uint64_t readIntRegOperand(const StaticInst *si, int idx)
| 252 IntReg readIntRegOperand(const StaticInst *si, int idx)
|
254 {
255 return this->cpu->readIntReg(this->_srcRegIdx[idx]);
256 }
257
258 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
259 {
260 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
261 }
262
263 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
264 {
265 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
266 }
267
| 253 {
254 return this->cpu->readIntReg(this->_srcRegIdx[idx]);
255 }
256
257 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
258 {
259 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
260 }
261
262 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
263 {
264 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
265 }
266
|
268 uint64_t readCCRegOperand(const StaticInst *si, int idx)
| 267 CCReg readCCRegOperand(const StaticInst *si, int idx)
|
269 {
270 return this->cpu->readCCReg(this->_srcRegIdx[idx]);
271 }
272
273 /** @todo: Make results into arrays so they can handle multiple dest
274 * registers.
275 */
| 268 {
269 return this->cpu->readCCReg(this->_srcRegIdx[idx]);
270 }
271
272 /** @todo: Make results into arrays so they can handle multiple dest
273 * registers.
274 */
|
276 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
| 275 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
|
277 {
278 this->cpu->setIntReg(this->_destRegIdx[idx], val);
279 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
280 }
281
282 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
283 {
284 this->cpu->setFloatReg(this->_destRegIdx[idx], val);
285 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
286 }
287
288 void setFloatRegOperandBits(const StaticInst *si, int idx,
289 FloatRegBits val)
290 {
291 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
292 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
293 }
294
| 276 {
277 this->cpu->setIntReg(this->_destRegIdx[idx], val);
278 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
279 }
280
281 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
282 {
283 this->cpu->setFloatReg(this->_destRegIdx[idx], val);
284 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
285 }
286
287 void setFloatRegOperandBits(const StaticInst *si, int idx,
288 FloatRegBits val)
289 {
290 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
291 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
292 }
293
|
295 void setCCRegOperand(const StaticInst *si, int idx, uint64_t val)
| 294 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
|
296 {
297 this->cpu->setCCReg(this->_destRegIdx[idx], val);
298 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
299 }
300
301#if THE_ISA == MIPS_ISA
| 295 {
296 this->cpu->setCCReg(this->_destRegIdx[idx], val);
297 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
298 }
299
300#if THE_ISA == MIPS_ISA
|
302 uint64_t readRegOtherThread(int misc_reg)
| 301 MiscReg readRegOtherThread(int misc_reg, ThreadID tid)
|
303 {
304 panic("MIPS MT not defined for O3 CPU.\n");
305 return 0;
306 }
307
| 302 {
303 panic("MIPS MT not defined for O3 CPU.\n");
304 return 0;
305 }
306
|
308 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
| 307 void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid)
|
309 {
310 panic("MIPS MT not defined for O3 CPU.\n");
311 }
312#endif
313
314 public:
315 /** Calculates EA part of a memory instruction. Currently unused,
316 * though it may be useful in the future if we want to split
317 * memory operations into EA calculation and memory access parts.
318 */
319 Fault calcEA()
320 {
321 return this->staticInst->eaCompInst()->execute(this, this->traceData);
322 }
323
324 /** Does the memory access part of a memory instruction. Currently unused,
325 * though it may be useful in the future if we want to split
326 * memory operations into EA calculation and memory access parts.
327 */
328 Fault memAccess()
329 {
330 return this->staticInst->memAccInst()->execute(this, this->traceData);
331 }
332};
333
334#endif // __CPU_O3_ALPHA_DYN_INST_HH__
335
| 308 {
309 panic("MIPS MT not defined for O3 CPU.\n");
310 }
311#endif
312
313 public:
314 /** Calculates EA part of a memory instruction. Currently unused,
315 * though it may be useful in the future if we want to split
316 * memory operations into EA calculation and memory access parts.
317 */
318 Fault calcEA()
319 {
320 return this->staticInst->eaCompInst()->execute(this, this->traceData);
321 }
322
323 /** Does the memory access part of a memory instruction. Currently unused,
324 * though it may be useful in the future if we want to split
325 * memory operations into EA calculation and memory access parts.
326 */
327 Fault memAccess()
328 {
329 return this->staticInst->memAccInst()->execute(this, this->traceData);
330 }
331};
332
333#endif // __CPU_O3_ALPHA_DYN_INST_HH__
334
|