dyn_inst.hh (13830:b5d6aa6c0e99) | dyn_inst.hh (13900:d4bcfecd871e) |
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1/* 2 * Copyright (c) 2010, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 415 unchanged lines hidden (view full) --- 424 BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val); 425 } 426 427 void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override 428 { 429 this->cpu->setCCReg(this->_destRegIdx[idx], val); 430 BaseDynInst<Impl>::setCCRegOperand(si, idx, val); 431 } | 1/* 2 * Copyright (c) 2010, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 415 unchanged lines hidden (view full) --- 424 BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val); 425 } 426 427 void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override 428 { 429 this->cpu->setCCReg(this->_destRegIdx[idx], val); 430 BaseDynInst<Impl>::setCCRegOperand(si, idx, val); 431 } |
432 433#if THE_ISA == MIPS_ISA 434 RegVal 435 readRegOtherThread(const RegId& misc_reg, ThreadID tid) override 436 { 437 panic("MIPS MT not defined for O3 CPU.\n"); 438 return 0; 439 } 440 441 void 442 setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) override 443 { 444 panic("MIPS MT not defined for O3 CPU.\n"); 445 } 446#endif | |
447}; 448 449#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 450 | 432}; 433 434#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 435 |