1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_DYN_INST_HH__
44#define __CPU_O3_DYN_INST_HH__
45
46#include "arch/isa_traits.hh"
47#include "config/the_isa.hh"
48#include "cpu/base_dyn_inst.hh"
49#include "cpu/inst_seq.hh"
50#include "cpu/o3/cpu.hh"
51#include "cpu/o3/isa_specific.hh"
52
53class Packet;
54
55/**
56 * Mostly implementation & ISA specific AlphaDynInst. As with most
57 * other classes in the new CPU model, it is templated on the Impl to
58 * allow for passing in of all types, such as the CPU type and the ISA
59 * type. The AlphaDynInst serves as the primary interface to the CPU
60 * for instructions that are executing.
61 */
62template <class Impl>
63class BaseO3DynInst : public BaseDynInst<Impl>
64{
65 public:
66 /** Typedef for the CPU. */
67 typedef typename Impl::O3CPU O3CPU;
68
69 /** Binary machine instruction type. */
70 typedef TheISA::MachInst MachInst;
71 /** Extended machine instruction type. */
72 typedef TheISA::ExtMachInst ExtMachInst;
73 /** Logical register index type. */
74 typedef TheISA::RegIndex RegIndex;
75 /** Integer register index type. */
76 typedef TheISA::IntReg IntReg;
77 typedef TheISA::FloatReg FloatReg;
78 typedef TheISA::FloatRegBits FloatRegBits;
79 /** Misc register index type. */
80 typedef TheISA::MiscReg MiscReg;
81
82 enum {
83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
84 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
85 };
86
87 public:
88 /** BaseDynInst constructor given a binary instruction. */
89 BaseO3DynInst(StaticInstPtr staticInst,
90 TheISA::PCState pc, TheISA::PCState predPC,
91 InstSeqNum seq_num, O3CPU *cpu);
92
93 /** BaseDynInst constructor given a binary instruction. */
94 BaseO3DynInst(ExtMachInst inst,
95 TheISA::PCState pc, TheISA::PCState predPC,
96 InstSeqNum seq_num, O3CPU *cpu);
97
98 /** BaseDynInst constructor given a static inst pointer. */
99 BaseO3DynInst(StaticInstPtr &_staticInst);
100
101 /** Executes the instruction.*/
102 Fault execute();
103
104 /** Initiates the access. Only valid for memory operations. */
105 Fault initiateAcc();
106
107 /** Completes the access. Only valid for memory operations. */
108 Fault completeAcc(PacketPtr pkt);
109
110 private:
111 /** Initializes variables. */
112 void initVars();
113
114 protected:
115 /** Indexes of the destination misc. registers. They are needed to defer
116 * the write accesses to the misc. registers until the commit stage, when
117 * the instruction is out of its speculative state.
118 */
119 int _destMiscRegIdx[MaxInstDestRegs];
120 /** Values to be written to the destination misc. registers. */
121 MiscReg _destMiscRegVal[MaxInstDestRegs];
122 /** Number of destination misc. registers. */
123 int _numDestMiscRegs;
124
125 public:
126 /** Reads a misc. register, including any side-effects the read
127 * might have as defined by the architecture.
128 */
129 MiscReg readMiscReg(int misc_reg)
130 {
131 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
132 }
133
134 /** Sets a misc. register, including any side-effects the write
135 * might have as defined by the architecture.
136 */
137 void setMiscReg(int misc_reg, const MiscReg &val)
138 {
139 /** Writes to misc. registers are recorded and deferred until the
140 * commit stage, when updateMiscRegs() is called.
141 */
142 _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
143 _destMiscRegVal[_numDestMiscRegs] = val;
144 _numDestMiscRegs++;
145 }
146
147 /** Reads a misc. register, including any side-effects the read
148 * might have as defined by the architecture.
149 */
150 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
151 {
152 return this->cpu->readMiscReg(
153 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
154 this->threadNumber);
155 }
156
157 /** Sets a misc. register, including any side-effects the write
158 * might have as defined by the architecture.
159 */
160 void setMiscRegOperand(const StaticInst *si, int idx,
161 const MiscReg &val)
162 {
163 int misc_reg = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
164 setMiscReg(misc_reg, val);
165 }
166
167 /** Called at the commit stage to update the misc. registers. */
168 void updateMiscRegs()
169 {
170 // @todo: Pretty convoluted way to avoid squashing from happening when
171 // using the TC during an instruction's execution (specifically for
172 // instructions that have side-effects that use the TC). Fix this.
173 // See cpu/o3/dyn_inst_impl.hh.
174 bool in_syscall = this->thread->inSyscall;
175 this->thread->inSyscall = true;
176
177 for (int i = 0; i < _numDestMiscRegs; i++)
178 this->cpu->setMiscReg(
179 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
180
181 this->thread->inSyscall = in_syscall;
182 }
183
184#if FULL_SYSTEM
185 /** Calls hardware return from error interrupt. */
186 Fault hwrei();
187 /** Traps to handle specified fault. */
188 void trap(Fault fault);
189 bool simPalCheck(int palFunc);
190#else
191 /** Calls a syscall. */
192 void syscall(int64_t callnum);
193#endif
194
195 public:
196
197 // The register accessor methods provide the index of the
198 // instruction's operand (e.g., 0 or 1), not the architectural
199 // register index, to simplify the implementation of register
200 // renaming. We find the architectural register index by indexing
201 // into the instruction's own operand index table. Note that a
202 // raw pointer to the StaticInst is provided instead of a
203 // ref-counted StaticInstPtr to redice overhead. This is fine as
204 // long as these methods don't copy the pointer into any long-term
205 // storage (which is pretty hard to imagine they would have reason
206 // to do).
207
208 uint64_t readIntRegOperand(const StaticInst *si, int idx)
209 {
210 return this->cpu->readIntReg(this->_srcRegIdx[idx]);
211 }
212
213 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
214 {
215 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
216 }
217
218 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
219 {
220 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
221 }
222
223 /** @todo: Make results into arrays so they can handle multiple dest
224 * registers.
225 */
226 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
227 {
228 this->cpu->setIntReg(this->_destRegIdx[idx], val);
229 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
230 }
231
232 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
233 {
234 this->cpu->setFloatReg(this->_destRegIdx[idx], val);
235 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
236 }
237
238 void setFloatRegOperandBits(const StaticInst *si, int idx,
239 FloatRegBits val)
240 {
241 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
242 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
243 }
244
245#if THE_ISA == MIPS_ISA
246 uint64_t readRegOtherThread(int misc_reg)
247 {
248 panic("MIPS MT not defined for O3 CPU.\n");
249 return 0;
250 }
251
252 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
253 {
254 panic("MIPS MT not defined for O3 CPU.\n");
255 }
256#endif
257
258 public:
259 /** Calculates EA part of a memory instruction. Currently unused,
260 * though it may be useful in the future if we want to split
261 * memory operations into EA calculation and memory access parts.
262 */
263 Fault calcEA()
264 {
265 return this->staticInst->eaCompInst()->execute(this, this->traceData);
266 }
267
268 /** Does the memory access part of a memory instruction. Currently unused,
269 * though it may be useful in the future if we want to split
270 * memory operations into EA calculation and memory access parts.
271 */
272 Fault memAccess()
273 {
274 return this->staticInst->memAccInst()->execute(this, this->traceData);
275 }
276};
277
278#endif // __CPU_O3_ALPHA_DYN_INST_HH__
279