1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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73 /** Extended machine instruction type. */
74 typedef TheISA::ExtMachInst ExtMachInst;
75 /** Logical register index type. */
76 typedef TheISA::RegIndex RegIndex;
77 /** Integer register index type. */
78 typedef TheISA::IntReg IntReg;
79 typedef TheISA::FloatReg FloatReg;
80 typedef TheISA::FloatRegBits FloatRegBits;
81 /** Misc register index type. */
82 typedef TheISA::MiscReg MiscReg;
83
84 enum {
85 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
86 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
87 };
88

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217 case IntRegClass:
218 this->setIntRegOperand(this->staticInst.get(), idx,
219 this->cpu->readIntReg(prev_phys_reg));
220 break;
221 case FloatRegClass:
222 this->setFloatRegOperandBits(this->staticInst.get(), idx,
223 this->cpu->readFloatRegBits(prev_phys_reg));
224 break;
225 case MiscRegClass:
226 // no need to forward misc reg values
227 break;
228 }
229 }
230 }
231 /** Calls hardware return from error interrupt. */
232 Fault hwrei();

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260 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
261 }
262
263 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
264 {
265 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
266 }
267
268 /** @todo: Make results into arrays so they can handle multiple dest
269 * registers.
270 */
271 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
272 {
273 this->cpu->setIntReg(this->_destRegIdx[idx], val);
274 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
275 }

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282
283 void setFloatRegOperandBits(const StaticInst *si, int idx,
284 FloatRegBits val)
285 {
286 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
287 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
288 }
289
290#if THE_ISA == MIPS_ISA
291 uint64_t readRegOtherThread(int misc_reg)
292 {
293 panic("MIPS MT not defined for O3 CPU.\n");
294 return 0;
295 }
296
297 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)

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