decode_impl.hh (8737:770ccf3af571) decode_impl.hh (8793:5f25086326ac)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "arch/types.hh"
32#include "base/trace.hh"
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "arch/types.hh"
32#include "base/trace.hh"
33#include "config/full_system.hh"
34#include "config/the_isa.hh"
35#include "cpu/o3/decode.hh"
36#include "cpu/inst_seq.hh"
37#include "debug/Activity.hh"
38#include "debug/Decode.hh"
39#include "params/DerivO3CPU.hh"
33#include "config/the_isa.hh"
34#include "cpu/o3/decode.hh"
35#include "cpu/inst_seq.hh"
36#include "debug/Activity.hh"
37#include "debug/Decode.hh"
38#include "params/DerivO3CPU.hh"
39#include "sim/full_system.hh"
40
40
41// clang complains about std::set being overloaded with Packet::set if
42// we open up the entire namespace std
43using std::list;
41using namespace std;
44
45template<class Impl>
46DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
47 : cpu(_cpu),
48 renameToDecodeDelay(params->renameToDecodeDelay),
49 iewToDecodeDelay(params->iewToDecodeDelay),
50 commitToDecodeDelay(params->commitToDecodeDelay),
51 fetchToDecodeDelay(params->fetchToDecodeDelay),

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319template<class Impl>
320unsigned
321DefaultDecode<Impl>::squash(ThreadID tid)
322{
323 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
324
325 if (decodeStatus[tid] == Blocked ||
326 decodeStatus[tid] == Unblocking) {
42
43template<class Impl>
44DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
45 : cpu(_cpu),
46 renameToDecodeDelay(params->renameToDecodeDelay),
47 iewToDecodeDelay(params->iewToDecodeDelay),
48 commitToDecodeDelay(params->commitToDecodeDelay),
49 fetchToDecodeDelay(params->fetchToDecodeDelay),

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317template<class Impl>
318unsigned
319DefaultDecode<Impl>::squash(ThreadID tid)
320{
321 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
322
323 if (decodeStatus[tid] == Blocked ||
324 decodeStatus[tid] == Unblocking) {
327#if !FULL_SYSTEM
328 // In syscall emulation, we can have both a block and a squash due
329 // to a syscall in the same cycle. This would cause both signals to
330 // be high. This shouldn't happen in full system.
331 // @todo: Determine if this still happens.
332 if (toFetch->decodeBlock[tid]) {
333 toFetch->decodeBlock[tid] = 0;
334 } else {
325 if (FullSystem) {
335 toFetch->decodeUnblock[tid] = 1;
326 toFetch->decodeUnblock[tid] = 1;
327 } else {
328 // In syscall emulation, we can have both a block and a squash due
329 // to a syscall in the same cycle. This would cause both signals
330 // to be high. This shouldn't happen in full system.
331 // @todo: Determine if this still happens.
332 if (toFetch->decodeBlock[tid])
333 toFetch->decodeBlock[tid] = 0;
334 else
335 toFetch->decodeUnblock[tid] = 1;
336 }
336 }
337#else
338 toFetch->decodeUnblock[tid] = 1;
339#endif
340 }
341
342 // Set status to squashing.
343 decodeStatus[tid] = Squashing;
344
345 // Go through incoming instructions from fetch and squash them.
346 unsigned squash_count = 0;
347

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444 }
445}
446
447template <class Impl>
448void
449DefaultDecode<Impl>::sortInsts()
450{
451 int insts_from_fetch = fromFetch->size;
337 }
338
339 // Set status to squashing.
340 decodeStatus[tid] = Squashing;
341
342 // Go through incoming instructions from fetch and squash them.
343 unsigned squash_count = 0;
344

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441 }
442}
443
444template <class Impl>
445void
446DefaultDecode<Impl>::sortInsts()
447{
448 int insts_from_fetch = fromFetch->size;
449#ifdef DEBUG
450 for (ThreadID tid = 0; tid < numThreads; tid++)
451 assert(insts[tid].empty());
452#endif
452 for (int i = 0; i < insts_from_fetch; ++i) {
453 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
454 }
455}
456
457template<class Impl>
458void
459DefaultDecode<Impl>::readStallSignals(ThreadID tid)

--- 299 unchanged lines hidden --- 		453 for (int i = 0; i < insts_from_fetch; ++i) {
454 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
455 }
456}
457
458template<class Impl>
459void
460DefaultDecode<Impl>::readStallSignals(ThreadID tid)

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