decode_impl.hh (4329:52057dbec096) | decode_impl.hh (4632:be5b8f67b8fb) |
---|---|
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 35 unchanged lines hidden (view full) --- 44 45 // Setup status, make sure stall signals are clear. 46 for (int i = 0; i < numThreads; ++i) { 47 decodeStatus[i] = Idle; 48 49 stalls[i].rename = false; 50 stalls[i].iew = false; 51 stalls[i].commit = false; | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 35 unchanged lines hidden (view full) --- 44 45 // Setup status, make sure stall signals are clear. 46 for (int i = 0; i < numThreads; ++i) { 47 decodeStatus[i] = Idle; 48 49 stalls[i].rename = false; 50 stalls[i].iew = false; 51 stalls[i].commit = false; |
52 53 squashAfterDelaySlot[i] = false; | |
54 } 55 56 // @todo: Make into a parameter 57 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 58} 59 60template <class Impl> 61std::string --- 211 unchanged lines hidden (view full) --- 273 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 274 ///FIXME There needs to be a way to set the nextPC and nextNPC 275 ///explicitly for ISAs with delay slots. 276 toFetch->decodeInfo[tid].nextNPC = 277 inst->branchTarget() + sizeof(TheISA::MachInst); 278#if ISA_HAS_DELAY_SLOT 279 toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() != 280 (inst->readNextPC() + sizeof(TheISA::MachInst)); | 52 } 53 54 // @todo: Make into a parameter 55 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 56} 57 58template <class Impl> 59std::string --- 211 unchanged lines hidden (view full) --- 271 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 272 ///FIXME There needs to be a way to set the nextPC and nextNPC 273 ///explicitly for ISAs with delay slots. 274 toFetch->decodeInfo[tid].nextNPC = 275 inst->branchTarget() + sizeof(TheISA::MachInst); 276#if ISA_HAS_DELAY_SLOT 277 toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() != 278 (inst->readNextPC() + sizeof(TheISA::MachInst)); |
281 282 toFetch->decodeInfo[tid].bdelayDoneSeqNum = bdelayDoneSeqNum[tid]; 283 squashAfterDelaySlot[tid] = false; 284 285 InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid]; | |
286#else 287 toFetch->decodeInfo[tid].branchTaken = 288 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); | 279#else 280 toFetch->decodeInfo[tid].branchTaken = 281 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); |
282#endif |
|
289 290 InstSeqNum squash_seq_num = inst->seqNum; | 283 284 InstSeqNum squash_seq_num = inst->seqNum; |
291#endif | |
292 293 // Might have to tell fetch to unblock. 294 if (decodeStatus[tid] == Blocked || 295 decodeStatus[tid] == Unblocking) { 296 toFetch->decodeUnblock[tid] = 1; 297 } 298 299 // Set status to squashing. --- 4 unchanged lines hidden (view full) --- 304 fromFetch->insts[i]->seqNum > squash_seq_num) { 305 fromFetch->insts[i]->setSquashed(); 306 } 307 } 308 309 // Clear the instruction list and skid buffer in case they have any 310 // insts in them. 311 while (!insts[tid].empty()) { | 285 286 // Might have to tell fetch to unblock. 287 if (decodeStatus[tid] == Blocked || 288 decodeStatus[tid] == Unblocking) { 289 toFetch->decodeUnblock[tid] = 1; 290 } 291 292 // Set status to squashing. --- 4 unchanged lines hidden (view full) --- 297 fromFetch->insts[i]->seqNum > squash_seq_num) { 298 fromFetch->insts[i]->setSquashed(); 299 } 300 } 301 302 // Clear the instruction list and skid buffer in case they have any 303 // insts in them. 304 while (!insts[tid].empty()) { |
312 313#if ISA_HAS_DELAY_SLOT 314 if (insts[tid].front()->seqNum <= squash_seq_num) { 315 DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode " 316 "instructions before delay slot [sn:%i]. %i insts" 317 "left in decode.\n", tid, squash_seq_num, 318 insts[tid].size()); 319 break; 320 } 321#endif | |
322 insts[tid].pop(); 323 } 324 325 while (!skidBuffer[tid].empty()) { | 305 insts[tid].pop(); 306 } 307 308 while (!skidBuffer[tid].empty()) { |
326 327#if ISA_HAS_DELAY_SLOT 328 if (skidBuffer[tid].front()->seqNum <= squash_seq_num) { 329 DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer " 330 "instructions before delay slot [sn:%i]. %i insts" 331 "left in decode.\n", tid, squash_seq_num, 332 insts[tid].size()); 333 break; 334 } 335#endif | |
336 skidBuffer[tid].pop(); 337 } 338 339 // Squash instructions up until this one 340 cpu->removeInstsUntil(squash_seq_num, tid); 341} 342 343template<class Impl> --- 411 unchanged lines hidden (view full) --- 755 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 756 ++decodeBranchResolved; 757 758 if (inst->branchTarget() != inst->readPredPC()) { 759 ++decodeBranchMispred; 760 761 // Might want to set some sort of boolean and just do 762 // a check at the end | 309 skidBuffer[tid].pop(); 310 } 311 312 // Squash instructions up until this one 313 cpu->removeInstsUntil(squash_seq_num, tid); 314} 315 316template<class Impl> --- 411 unchanged lines hidden (view full) --- 728 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 729 ++decodeBranchResolved; 730 731 if (inst->branchTarget() != inst->readPredPC()) { 732 ++decodeBranchMispred; 733 734 // Might want to set some sort of boolean and just do 735 // a check at the end |
763#if !ISA_HAS_DELAY_SLOT | |
764 squash(inst, inst->threadNumber); 765 Addr target = inst->branchTarget(); 766 inst->setPredTarg(target, target + sizeof(TheISA::MachInst)); 767 break; | 736 squash(inst, inst->threadNumber); 737 Addr target = inst->branchTarget(); 738 inst->setPredTarg(target, target + sizeof(TheISA::MachInst)); 739 break; |
768#else 769 // If mispredicted as taken, then ignore delay slot 770 // instruction... else keep delay slot and squash 771 // after it is sent to rename 772 if (inst->readPredTaken() && inst->isCondDelaySlot()) { 773 DPRINTF(Decode, "[tid:%i]: Conditional delay slot inst." 774 "[sn:%i] PC %#x mispredicted as taken.\n", tid, 775 inst->seqNum, inst->PC); 776 bdelayDoneSeqNum[tid] = inst->seqNum; 777 squash(inst, inst->threadNumber); 778 Addr target = inst->branchTarget(); 779 inst->setPredTarg(target, 780 target + sizeof(TheISA::MachInst)); 781 break; 782 } else { 783 DPRINTF(Decode, "[tid:%i]: Misprediction detected at " 784 "[sn:%i] PC %#x, will squash after delay slot " 785 "inst. is sent to Rename\n", 786 tid, inst->seqNum, inst->PC); 787 bdelayDoneSeqNum[tid] = inst->seqNum + 1; 788 squashAfterDelaySlot[tid] = true; 789 squashInst[tid] = inst; 790 continue; 791 } 792#endif | |
793 } 794 } | 740 } 741 } |
795 796 if (squashAfterDelaySlot[tid]) { 797 assert(!inst->isSquashed()); 798 squash(squashInst[tid], squashInst[tid]->threadNumber); 799 Addr target = squashInst[tid]->branchTarget(); 800 squashInst[tid]->setPredTarg(target, 801 target + sizeof(TheISA::MachInst)); 802 assert(!inst->isSquashed()); 803 break; 804 } | |
805 } 806 807 // If we didn't process all instructions, then we will need to block 808 // and put all those instructions into the skid buffer. 809 if (!insts_to_decode.empty()) { 810 block(tid); 811 } 812 813 // Record that decode has written to the time buffer for activity 814 // tracking. 815 if (toRenameIndex) { 816 wroteToTimeBuffer = true; 817 } 818} | 742 } 743 744 // If we didn't process all instructions, then we will need to block 745 // and put all those instructions into the skid buffer. 746 if (!insts_to_decode.empty()) { 747 block(tid); 748 } 749 750 // Record that decode has written to the time buffer for activity 751 // tracking. 752 if (toRenameIndex) { 753 wroteToTimeBuffer = true; 754 } 755} |