decode_impl.hh (3093:b09c33e66bce) | decode_impl.hh (3796:9cb1eaf3a461) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 727 unchanged lines hidden (view full) --- 736 737 ++(toRename->size); 738 ++toRenameIndex; 739 ++decodeDecodedInsts; 740 --insts_available; 741 742 // Ensure that if it was predicted as a branch, it really is a 743 // branch. | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 727 unchanged lines hidden (view full) --- 736 737 ++(toRename->size); 738 ++toRenameIndex; 739 ++decodeDecodedInsts; 740 --insts_available; 741 742 // Ensure that if it was predicted as a branch, it really is a 743 // branch. |
744 if (inst->predTaken() && !inst->isControl()) { | 744 if (inst->readPredTaken() && !inst->isControl()) { |
745 DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n",inst->predPC, 746 inst->nextPC + 4); 747 748 panic("Instruction predicted as a branch!"); 749 750 ++decodeControlMispred; 751 752 // Might want to set some sort of boolean and just do 753 // a check at the end 754 squash(inst, inst->threadNumber); 755 756 break; 757 } 758 759 // Go ahead and compute any PC-relative branches. 760 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 761 ++decodeBranchResolved; 762 | 745 DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n",inst->predPC, 746 inst->nextPC + 4); 747 748 panic("Instruction predicted as a branch!"); 749 750 ++decodeControlMispred; 751 752 // Might want to set some sort of boolean and just do 753 // a check at the end 754 squash(inst, inst->threadNumber); 755 756 break; 757 } 758 759 // Go ahead and compute any PC-relative branches. 760 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 761 ++decodeBranchResolved; 762 |
763 if (inst->branchTarget() != inst->readPredTarg()) { | 763 if (inst->branchTarget() != inst->readPredPC()) { |
764 ++decodeBranchMispred; 765 766 // Might want to set some sort of boolean and just do 767 // a check at the end 768#if !ISA_HAS_DELAY_SLOT 769 squash(inst, inst->threadNumber); | 764 ++decodeBranchMispred; 765 766 // Might want to set some sort of boolean and just do 767 // a check at the end 768#if !ISA_HAS_DELAY_SLOT 769 squash(inst, inst->threadNumber); |
770 inst->setPredTarg(inst->branchTarget()); | 770 Addr target = inst->branchTarget(); 771 inst->setPredTarg(target, target + sizeof(TheISA::MachInst)); |
771 break; 772#else 773 // If mispredicted as taken, then ignore delay slot 774 // instruction... else keep delay slot and squash 775 // after it is sent to rename | 772 break; 773#else 774 // If mispredicted as taken, then ignore delay slot 775 // instruction... else keep delay slot and squash 776 // after it is sent to rename |
776 if (inst->predTaken() && inst->isCondDelaySlot()) { | 777 if (inst->readPredTaken() && inst->isCondDelaySlot()) { |
777 DPRINTF(Decode, "[tid:%i]: Conditional delay slot inst." 778 "[sn:%i] PC %#x mispredicted as taken.\n", tid, 779 inst->seqNum, inst->PC); 780 bdelayDoneSeqNum[tid] = inst->seqNum; 781 squash(inst, inst->threadNumber); | 778 DPRINTF(Decode, "[tid:%i]: Conditional delay slot inst." 779 "[sn:%i] PC %#x mispredicted as taken.\n", tid, 780 inst->seqNum, inst->PC); 781 bdelayDoneSeqNum[tid] = inst->seqNum; 782 squash(inst, inst->threadNumber); |
782 inst->setPredTarg(inst->branchTarget()); | 783 Addr target = inst->branchTarget(); 784 inst->setPredTarg(target, 785 target + sizeof(TheISA::MachInst)); |
783 break; 784 } else { 785 DPRINTF(Decode, "[tid:%i]: Misprediction detected at " 786 "[sn:%i] PC %#x, will squash after delay slot " 787 "inst. is sent to Rename\n", 788 tid, inst->seqNum, inst->PC); 789 bdelayDoneSeqNum[tid] = inst->seqNum + 1; 790 squashAfterDelaySlot[tid] = true; 791 squashInst[tid] = inst; 792 continue; 793 } 794#endif 795 } 796 } 797 798 if (squashAfterDelaySlot[tid]) { 799 assert(!inst->isSquashed()); 800 squash(squashInst[tid], squashInst[tid]->threadNumber); | 786 break; 787 } else { 788 DPRINTF(Decode, "[tid:%i]: Misprediction detected at " 789 "[sn:%i] PC %#x, will squash after delay slot " 790 "inst. is sent to Rename\n", 791 tid, inst->seqNum, inst->PC); 792 bdelayDoneSeqNum[tid] = inst->seqNum + 1; 793 squashAfterDelaySlot[tid] = true; 794 squashInst[tid] = inst; 795 continue; 796 } 797#endif 798 } 799 } 800 801 if (squashAfterDelaySlot[tid]) { 802 assert(!inst->isSquashed()); 803 squash(squashInst[tid], squashInst[tid]->threadNumber); |
801 squashInst[tid]->setPredTarg(squashInst[tid]->branchTarget()); | 804 Addr target = squashInst[tid]->branchTarget(); 805 squashInst[tid]->setPredTarg(target, 806 target + sizeof(TheISA::MachInst)); |
802 assert(!inst->isSquashed()); 803 break; 804 } 805 } 806 807 // If we didn't process all instructions, then we will need to block 808 // and put all those instructions into the skid buffer. 809 if (!insts_to_decode.empty()) { 810 block(tid); 811 } 812 813 // Record that decode has written to the time buffer for activity 814 // tracking. 815 if (toRenameIndex) { 816 wroteToTimeBuffer = true; 817 } 818} | 807 assert(!inst->isSquashed()); 808 break; 809 } 810 } 811 812 // If we didn't process all instructions, then we will need to block 813 // and put all those instructions into the skid buffer. 814 if (!insts_to_decode.empty()) { 815 block(tid); 816 } 817 818 // Record that decode has written to the time buffer for activity 819 // tracking. 820 if (toRenameIndex) { 821 wroteToTimeBuffer = true; 822 } 823} |