decode_impl.hh (2980:eab855f06b79) decode_impl.hh (3093:b09c33e66bce)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 268 unchanged lines hidden (view full) ---

277 "detected at decode.\n", tid);
278
279 // Send back mispredict information.
280 toFetch->decodeInfo[tid].branchMispredict = true;
281 toFetch->decodeInfo[tid].predIncorrect = true;
282 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
283 toFetch->decodeInfo[tid].squash = true;
284 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 268 unchanged lines hidden (view full) ---

277 "detected at decode.\n", tid);
278
279 // Send back mispredict information.
280 toFetch->decodeInfo[tid].branchMispredict = true;
281 toFetch->decodeInfo[tid].predIncorrect = true;
282 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
283 toFetch->decodeInfo[tid].squash = true;
284 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
285#if THE_ISA == ALPHA_ISA
286 toFetch->decodeInfo[tid].branchTaken =
287 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
288
289 InstSeqNum squash_seq_num = inst->seqNum;
290#else
285#if ISA_HAS_DELAY_SLOT
291 toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() !=
292 (inst->readNextPC() + sizeof(TheISA::MachInst));
293
294 toFetch->decodeInfo[tid].bdelayDoneSeqNum = bdelayDoneSeqNum[tid];
295 squashAfterDelaySlot[tid] = false;
296
297 InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid];
286 toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() !=
287 (inst->readNextPC() + sizeof(TheISA::MachInst));
288
289 toFetch->decodeInfo[tid].bdelayDoneSeqNum = bdelayDoneSeqNum[tid];
290 squashAfterDelaySlot[tid] = false;
291
292 InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid];
293#else
294 toFetch->decodeInfo[tid].branchTaken =
295 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
296
297 InstSeqNum squash_seq_num = inst->seqNum;
298#endif
299
300 // Might have to tell fetch to unblock.
301 if (decodeStatus[tid] == Blocked ||
302 decodeStatus[tid] == Unblocking) {
303 toFetch->decodeUnblock[tid] = 1;
304 }
305

--- 6 unchanged lines hidden (view full) ---

312 fromFetch->insts[i]->setSquashed();
313 }
314 }
315
316 // Clear the instruction list and skid buffer in case they have any
317 // insts in them.
318 while (!insts[tid].empty()) {
319
298#endif
299
300 // Might have to tell fetch to unblock.
301 if (decodeStatus[tid] == Blocked ||
302 decodeStatus[tid] == Unblocking) {
303 toFetch->decodeUnblock[tid] = 1;
304 }
305

--- 6 unchanged lines hidden (view full) ---

312 fromFetch->insts[i]->setSquashed();
313 }
314 }
315
316 // Clear the instruction list and skid buffer in case they have any
317 // insts in them.
318 while (!insts[tid].empty()) {
319
320#if THE_ISA != ALPHA_ISA
320#if ISA_HAS_DELAY_SLOT
321 if (insts[tid].front()->seqNum <= squash_seq_num) {
322 DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode "
323 "instructions before delay slot [sn:%i]. %i insts"
324 "left in decode.\n", tid, squash_seq_num,
325 insts[tid].size());
326 break;
327 }
328#endif
329 insts[tid].pop();
330 }
331
332 while (!skidBuffer[tid].empty()) {
333
321 if (insts[tid].front()->seqNum <= squash_seq_num) {
322 DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode "
323 "instructions before delay slot [sn:%i]. %i insts"
324 "left in decode.\n", tid, squash_seq_num,
325 insts[tid].size());
326 break;
327 }
328#endif
329 insts[tid].pop();
330 }
331
332 while (!skidBuffer[tid].empty()) {
333
334#if THE_ISA != ALPHA_ISA
334#if ISA_HAS_DELAY_SLOT
335 if (skidBuffer[tid].front()->seqNum <= squash_seq_num) {
336 DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer "
337 "instructions before delay slot [sn:%i]. %i insts"
338 "left in decode.\n", tid, squash_seq_num,
339 insts[tid].size());
340 break;
341 }
342#endif

--- 417 unchanged lines hidden (view full) ---

760 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
761 ++decodeBranchResolved;
762
763 if (inst->branchTarget() != inst->readPredTarg()) {
764 ++decodeBranchMispred;
765
766 // Might want to set some sort of boolean and just do
767 // a check at the end
335 if (skidBuffer[tid].front()->seqNum <= squash_seq_num) {
336 DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer "
337 "instructions before delay slot [sn:%i]. %i insts"
338 "left in decode.\n", tid, squash_seq_num,
339 insts[tid].size());
340 break;
341 }
342#endif

--- 417 unchanged lines hidden (view full) ---

760 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
761 ++decodeBranchResolved;
762
763 if (inst->branchTarget() != inst->readPredTarg()) {
764 ++decodeBranchMispred;
765
766 // Might want to set some sort of boolean and just do
767 // a check at the end
768#if THE_ISA == ALPHA_ISA
768#if !ISA_HAS_DELAY_SLOT
769 squash(inst, inst->threadNumber);
770 inst->setPredTarg(inst->branchTarget());
771 break;
772#else
773 // If mispredicted as taken, then ignore delay slot
774 // instruction... else keep delay slot and squash
775 // after it is sent to rename
776 if (inst->predTaken() && inst->isCondDelaySlot()) {

--- 42 unchanged lines hidden --- 		769 squash(inst, inst->threadNumber);
770 inst->setPredTarg(inst->branchTarget());
771 break;
772#else
773 // If mispredicted as taken, then ignore delay slot
774 // instruction... else keep delay slot and squash
775 // after it is sent to rename
776 if (inst->predTaken() && inst->isCondDelaySlot()) {

--- 42 unchanged lines hidden ---