decode_impl.hh (2674:6d4afef73a20) decode_impl.hh (2678:1f86b91dc3bb)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 266 unchanged lines hidden (view full) ---

275 DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction "
276 "detected at decode.\n", tid);
277
278 // Send back mispredict information.
279 toFetch->decodeInfo[tid].branchMispredict = true;
280 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
281 toFetch->decodeInfo[tid].predIncorrect = true;
282 toFetch->decodeInfo[tid].squash = true;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 266 unchanged lines hidden (view full) ---

275 DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction "
276 "detected at decode.\n", tid);
277
278 // Send back mispredict information.
279 toFetch->decodeInfo[tid].branchMispredict = true;
280 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
281 toFetch->decodeInfo[tid].predIncorrect = true;
282 toFetch->decodeInfo[tid].squash = true;
283 toFetch->decodeInfo[tid].nextPC = inst->readNextPC();
283 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
284 toFetch->decodeInfo[tid].branchTaken =
285 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
286
287 // Might have to tell fetch to unblock.
288 if (decodeStatus[tid] == Blocked ||
289 decodeStatus[tid] == Unblocking) {
290 toFetch->decodeUnblock[tid] = 1;
291 }

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718 squash(inst, inst->threadNumber);
719
720 break;
721 }
722
723 // Go ahead and compute any PC-relative branches.
724 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
725 ++decodeBranchResolved;
284 toFetch->decodeInfo[tid].branchTaken =
285 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
286
287 // Might have to tell fetch to unblock.
288 if (decodeStatus[tid] == Blocked ||
289 decodeStatus[tid] == Unblocking) {
290 toFetch->decodeUnblock[tid] = 1;
291 }

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718 squash(inst, inst->threadNumber);
719
720 break;
721 }
722
723 // Go ahead and compute any PC-relative branches.
724 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
725 ++decodeBranchResolved;
726 inst->setNextPC(inst->branchTarget());
727
726
728 if (inst->mispredicted()) {
727 if (inst->branchTarget() != inst->readPredTarg()) {
729 ++decodeBranchMispred;
730
731 // Might want to set some sort of boolean and just do
732 // a check at the end
733 squash(inst, inst->threadNumber);
734 inst->setPredTarg(inst->branchTarget());
735
736 break;

--- 16 unchanged lines hidden --- 		728 ++decodeBranchMispred;
729
730 // Might want to set some sort of boolean and just do
731 // a check at the end
732 squash(inst, inst->threadNumber);
733 inst->setPredTarg(inst->branchTarget());
734
735 break;

--- 16 unchanged lines hidden ---