14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include "arch/types.hh"
44#include "base/trace.hh"
45#include "config/the_isa.hh"
46#include "cpu/o3/decode.hh"
47#include "cpu/inst_seq.hh"
48#include "debug/Activity.hh"
49#include "debug/Decode.hh"
50#include "params/DerivO3CPU.hh"
51#include "sim/full_system.hh"
52
53// clang complains about std::set being overloaded with Packet::set if
54// we open up the entire namespace std
55using std::list;
56
57template<class Impl>
58DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
59 : cpu(_cpu),
60 renameToDecodeDelay(params->renameToDecodeDelay),
61 iewToDecodeDelay(params->iewToDecodeDelay),
62 commitToDecodeDelay(params->commitToDecodeDelay),
63 fetchToDecodeDelay(params->fetchToDecodeDelay),
64 decodeWidth(params->decodeWidth),
65 numThreads(params->numThreads)
66{
|
198}
199
200template<class Impl>
201bool
202DefaultDecode<Impl>::checkStall(ThreadID tid) const
203{
204 bool ret_val = false;
205
206 if (stalls[tid].rename) {
207 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
208 ret_val = true;
209 } else if (stalls[tid].iew) {
210 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
211 ret_val = true;
212 } else if (stalls[tid].commit) {
213 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
214 ret_val = true;
215 }
216
217 return ret_val;
218}
219
220template<class Impl>
221inline bool
222DefaultDecode<Impl>::fetchInstsValid()
223{
224 return fromFetch->size > 0;
225}
226
227template<class Impl>
228bool
229DefaultDecode<Impl>::block(ThreadID tid)
230{
231 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
232
233 // Add the current inputs to the skid buffer so they can be
234 // reprocessed when this stage unblocks.
235 skidInsert(tid);
236
237 // If the decode status is blocked or unblocking then decode has not yet
238 // signalled fetch to unblock. In that case, there is no need to tell
239 // fetch to block.
240 if (decodeStatus[tid] != Blocked) {
241 // Set the status to Blocked.
242 decodeStatus[tid] = Blocked;
243
244 if (decodeStatus[tid] != Unblocking) {
245 toFetch->decodeBlock[tid] = true;
246 wroteToTimeBuffer = true;
247 }
248
249 return true;
250 }
251
252 return false;
253}
254
255template<class Impl>
256bool
257DefaultDecode<Impl>::unblock(ThreadID tid)
258{
259 // Decode is done unblocking only if the skid buffer is empty.
260 if (skidBuffer[tid].empty()) {
261 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
262 toFetch->decodeUnblock[tid] = true;
263 wroteToTimeBuffer = true;
264
265 decodeStatus[tid] = Running;
266 return true;
267 }
268
269 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
270
271 return false;
272}
273
274template<class Impl>
275void
276DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
277{
278 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch "
279 "prediction detected at decode.\n", tid, inst->seqNum);
280
281 // Send back mispredict information.
282 toFetch->decodeInfo[tid].branchMispredict = true;
283 toFetch->decodeInfo[tid].predIncorrect = true;
284 toFetch->decodeInfo[tid].mispredictInst = inst;
285 toFetch->decodeInfo[tid].squash = true;
286 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
287 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
288 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
289 toFetch->decodeInfo[tid].squashInst = inst;
290 if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) {
291 toFetch->decodeInfo[tid].branchTaken = true;
292 }
293
294 InstSeqNum squash_seq_num = inst->seqNum;
295
296 // Might have to tell fetch to unblock.
297 if (decodeStatus[tid] == Blocked ||
298 decodeStatus[tid] == Unblocking) {
299 toFetch->decodeUnblock[tid] = 1;
300 }
301
302 // Set status to squashing.
303 decodeStatus[tid] = Squashing;
304
305 for (int i=0; i<fromFetch->size; i++) {
306 if (fromFetch->insts[i]->threadNumber == tid &&
307 fromFetch->insts[i]->seqNum > squash_seq_num) {
308 fromFetch->insts[i]->setSquashed();
309 }
310 }
311
312 // Clear the instruction list and skid buffer in case they have any
313 // insts in them.
314 while (!insts[tid].empty()) {
315 insts[tid].pop();
316 }
317
318 while (!skidBuffer[tid].empty()) {
319 skidBuffer[tid].pop();
320 }
321
322 // Squash instructions up until this one
323 cpu->removeInstsUntil(squash_seq_num, tid);
324}
325
326template<class Impl>
327unsigned
328DefaultDecode<Impl>::squash(ThreadID tid)
329{
330 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
331
332 if (decodeStatus[tid] == Blocked ||
333 decodeStatus[tid] == Unblocking) {
334 if (FullSystem) {
335 toFetch->decodeUnblock[tid] = 1;
336 } else {
337 // In syscall emulation, we can have both a block and a squash due
338 // to a syscall in the same cycle. This would cause both signals
339 // to be high. This shouldn't happen in full system.
340 // @todo: Determine if this still happens.
341 if (toFetch->decodeBlock[tid])
342 toFetch->decodeBlock[tid] = 0;
343 else
344 toFetch->decodeUnblock[tid] = 1;
345 }
346 }
347
348 // Set status to squashing.
349 decodeStatus[tid] = Squashing;
350
351 // Go through incoming instructions from fetch and squash them.
352 unsigned squash_count = 0;
353
354 for (int i=0; i<fromFetch->size; i++) {
355 if (fromFetch->insts[i]->threadNumber == tid) {
356 fromFetch->insts[i]->setSquashed();
357 squash_count++;
358 }
359 }
360
361 // Clear the instruction list and skid buffer in case they have any
362 // insts in them.
363 while (!insts[tid].empty()) {
364 insts[tid].pop();
365 }
366
367 while (!skidBuffer[tid].empty()) {
368 skidBuffer[tid].pop();
369 }
370
371 return squash_count;
372}
373
374template<class Impl>
375void
376DefaultDecode<Impl>::skidInsert(ThreadID tid)
377{
378 DynInstPtr inst = NULL;
379
380 while (!insts[tid].empty()) {
381 inst = insts[tid].front();
382
383 insts[tid].pop();
384
385 assert(tid == inst->threadNumber);
386
387 DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n",
388 inst->seqNum, inst->pcState(), inst->threadNumber);
389
390 skidBuffer[tid].push(inst);
391 }
392
393 // @todo: Eventually need to enforce this by not letting a thread
394 // fetch past its skidbuffer
395 assert(skidBuffer[tid].size() <= skidBufferMax);
396}
397
398template<class Impl>
399bool
400DefaultDecode<Impl>::skidsEmpty()
401{
402 list<ThreadID>::iterator threads = activeThreads->begin();
403 list<ThreadID>::iterator end = activeThreads->end();
404
405 while (threads != end) {
406 ThreadID tid = *threads++;
407 if (!skidBuffer[tid].empty())
408 return false;
409 }
410
411 return true;
412}
413
414template<class Impl>
415void
416DefaultDecode<Impl>::updateStatus()
417{
418 bool any_unblocking = false;
419
420 list<ThreadID>::iterator threads = activeThreads->begin();
421 list<ThreadID>::iterator end = activeThreads->end();
422
423 while (threads != end) {
424 ThreadID tid = *threads++;
425
426 if (decodeStatus[tid] == Unblocking) {
427 any_unblocking = true;
428 break;
429 }
430 }
431
432 // Decode will have activity if it's unblocking.
433 if (any_unblocking) {
434 if (_status == Inactive) {
435 _status = Active;
436
437 DPRINTF(Activity, "Activating stage.\n");
438
439 cpu->activateStage(O3CPU::DecodeIdx);
440 }
441 } else {
442 // If it's not unblocking, then decode will not have any internal
443 // activity. Switch it to inactive.
444 if (_status == Active) {
445 _status = Inactive;
446 DPRINTF(Activity, "Deactivating stage.\n");
447
448 cpu->deactivateStage(O3CPU::DecodeIdx);
449 }
450 }
451}
452
453template <class Impl>
454void
455DefaultDecode<Impl>::sortInsts()
456{
457 int insts_from_fetch = fromFetch->size;
458 for (int i = 0; i < insts_from_fetch; ++i) {
459 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
460 }
461}
462
463template<class Impl>
464void
465DefaultDecode<Impl>::readStallSignals(ThreadID tid)
466{
467 if (fromRename->renameBlock[tid]) {
468 stalls[tid].rename = true;
469 }
470
471 if (fromRename->renameUnblock[tid]) {
472 assert(stalls[tid].rename);
473 stalls[tid].rename = false;
474 }
475
476 if (fromIEW->iewBlock[tid]) {
477 stalls[tid].iew = true;
478 }
479
480 if (fromIEW->iewUnblock[tid]) {
481 assert(stalls[tid].iew);
482 stalls[tid].iew = false;
483 }
484
485 if (fromCommit->commitBlock[tid]) {
486 stalls[tid].commit = true;
487 }
488
489 if (fromCommit->commitUnblock[tid]) {
490 assert(stalls[tid].commit);
491 stalls[tid].commit = false;
492 }
493}
494
495template <class Impl>
496bool
497DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid)
498{
499 // Check if there's a squash signal, squash if there is.
500 // Check stall signals, block if necessary.
501 // If status was blocked
502 // Check if stall conditions have passed
503 // if so then go to unblocking
504 // If status was Squashing
505 // check if squashing is not high. Switch to running this cycle.
506
507 // Update the per thread stall statuses.
508 readStallSignals(tid);
509
510 // Check squash signals from commit.
511 if (fromCommit->commitInfo[tid].squash) {
512
513 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
514 "from commit.\n", tid);
515
516 squash(tid);
517
518 return true;
519 }
520
521 // Check ROB squash signals from commit.
522 if (fromCommit->commitInfo[tid].robSquashing) {
523 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
524
525 // Continue to squash.
526 decodeStatus[tid] = Squashing;
527
528 return true;
529 }
530
531 if (checkStall(tid)) {
532 return block(tid);
533 }
534
535 if (decodeStatus[tid] == Blocked) {
536 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
537 tid);
538
539 decodeStatus[tid] = Unblocking;
540
541 unblock(tid);
542
543 return true;
544 }
545
546 if (decodeStatus[tid] == Squashing) {
547 // Switch status to running if decode isn't being told to block or
548 // squash this cycle.
549 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
550 tid);
551
552 decodeStatus[tid] = Running;
553
554 return false;
555 }
556
557 // If we've reached this point, we have not gotten any signals that
558 // cause decode to change its status. Decode remains the same as before.
559 return false;
560}
561
562template<class Impl>
563void
564DefaultDecode<Impl>::tick()
565{
566 wroteToTimeBuffer = false;
567
568 bool status_change = false;
569
570 toRenameIndex = 0;
571
572 list<ThreadID>::iterator threads = activeThreads->begin();
573 list<ThreadID>::iterator end = activeThreads->end();
574
575 sortInsts();
576
577 //Check stall and squash signals.
578 while (threads != end) {
579 ThreadID tid = *threads++;
580
581 DPRINTF(Decode,"Processing [tid:%i]\n",tid);
582 status_change = checkSignalsAndUpdate(tid) || status_change;
583
584 decode(status_change, tid);
585 }
586
587 if (status_change) {
588 updateStatus();
589 }
590
591 if (wroteToTimeBuffer) {
592 DPRINTF(Activity, "Activity this cycle.\n");
593
594 cpu->activityThisCycle();
595 }
596}
597
598template<class Impl>
599void
600DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid)
601{
602 // If status is Running or idle,
603 // call decodeInsts()
604 // If status is Unblocking,
605 // buffer any instructions coming from fetch
606 // continue trying to empty skid buffer
607 // check if stall conditions have passed
608
609 if (decodeStatus[tid] == Blocked) {
610 ++decodeBlockedCycles;
611 } else if (decodeStatus[tid] == Squashing) {
612 ++decodeSquashCycles;
613 }
614
615 // Decode should try to decode as many instructions as its bandwidth
616 // will allow, as long as it is not currently blocked.
617 if (decodeStatus[tid] == Running ||
618 decodeStatus[tid] == Idle) {
619 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
620 "stage.\n",tid);
621
622 decodeInsts(tid);
623 } else if (decodeStatus[tid] == Unblocking) {
624 // Make sure that the skid buffer has something in it if the
625 // status is unblocking.
626 assert(!skidsEmpty());
627
628 // If the status was unblocking, then instructions from the skid
629 // buffer were used. Remove those instructions and handle
630 // the rest of unblocking.
631 decodeInsts(tid);
632
633 if (fetchInstsValid()) {
634 // Add the current inputs to the skid buffer so they can be
635 // reprocessed when this stage unblocks.
636 skidInsert(tid);
637 }
638
639 status_change = unblock(tid) || status_change;
640 }
641}
642
643template <class Impl>
644void
645DefaultDecode<Impl>::decodeInsts(ThreadID tid)
646{
647 // Instructions can come either from the skid buffer or the list of
648 // instructions coming from fetch, depending on decode's status.
649 int insts_available = decodeStatus[tid] == Unblocking ?
650 skidBuffer[tid].size() : insts[tid].size();
651
652 if (insts_available == 0) {
653 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
654 " early.\n",tid);
655 // Should I change the status to idle?
656 ++decodeIdleCycles;
657 return;
658 } else if (decodeStatus[tid] == Unblocking) {
659 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
660 "buffer.\n",tid);
661 ++decodeUnblockCycles;
662 } else if (decodeStatus[tid] == Running) {
663 ++decodeRunCycles;
664 }
665
666 DynInstPtr inst;
667
668 std::queue<DynInstPtr>
669 &insts_to_decode = decodeStatus[tid] == Unblocking ?
670 skidBuffer[tid] : insts[tid];
671
672 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
673
674 while (insts_available > 0 && toRenameIndex < decodeWidth) {
675 assert(!insts_to_decode.empty());
676
677 inst = insts_to_decode.front();
678
679 insts_to_decode.pop();
680
681 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
682 "PC %s\n", tid, inst->seqNum, inst->pcState());
683
684 if (inst->isSquashed()) {
685 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is "
686 "squashed, skipping.\n",
687 tid, inst->seqNum, inst->pcState());
688
689 ++decodeSquashedInsts;
690
691 --insts_available;
692
693 continue;
694 }
695
696 // Also check if instructions have no source registers. Mark
697 // them as ready to issue at any time. Not sure if this check
698 // should exist here or at a later stage; however it doesn't matter
699 // too much for function correctness.
700 if (inst->numSrcRegs() == 0) {
701 inst->setCanIssue();
702 }
703
704 // This current instruction is valid, so add it into the decode
705 // queue. The next instruction may not be valid, so check to
706 // see if branches were predicted correctly.
707 toRename->insts[toRenameIndex] = inst;
708
709 ++(toRename->size);
710 ++toRenameIndex;
711 ++decodeDecodedInsts;
712 --insts_available;
713
714#if TRACING_ON
715 inst->decodeTick = curTick() - inst->fetchTick;
716#endif
717
718 // Ensure that if it was predicted as a branch, it really is a
719 // branch.
720 if (inst->readPredTaken() && !inst->isControl()) {
721 panic("Instruction predicted as a branch!");
722
723 ++decodeControlMispred;
724
725 // Might want to set some sort of boolean and just do
726 // a check at the end
727 squash(inst, inst->threadNumber);
728
729 break;
730 }
731
732 // Go ahead and compute any PC-relative branches.
733 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
734 ++decodeBranchResolved;
735
736 if (!(inst->branchTarget() == inst->readPredTarg())) {
737 ++decodeBranchMispred;
738
739 // Might want to set some sort of boolean and just do
740 // a check at the end
741 squash(inst, inst->threadNumber);
742 TheISA::PCState target = inst->branchTarget();
743
744 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n",
745 inst->seqNum, target);
746 //The micro pc after an instruction level branch should be 0
747 inst->setPredTarg(target);
748 break;
749 }
750 }
751 }
752
753 // If we didn't process all instructions, then we will need to block
754 // and put all those instructions into the skid buffer.
755 if (!insts_to_decode.empty()) {
756 block(tid);
757 }
758
759 // Record that decode has written to the time buffer for activity
760 // tracking.
761 if (toRenameIndex) {
762 wroteToTimeBuffer = true;
763 }
764}
|