1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 33 unchanged lines hidden (view full) --- 42 43#include "arch/types.hh" 44#include "base/trace.hh" 45#include "config/the_isa.hh" 46#include "cpu/o3/decode.hh" 47#include "cpu/inst_seq.hh" 48#include "debug/Activity.hh" 49#include "debug/Decode.hh" |
50#include "debug/O3PipeView.hh" |
51#include "params/DerivO3CPU.hh" 52#include "sim/full_system.hh" 53 54// clang complains about std::set being overloaded with Packet::set if 55// we open up the entire namespace std 56using std::list; 57 58template<class Impl> --- 651 unchanged lines hidden (view full) --- 710 toRename->insts[toRenameIndex] = inst; 711 712 ++(toRename->size); 713 ++toRenameIndex; 714 ++decodeDecodedInsts; 715 --insts_available; 716 717#if TRACING_ON |
718 if (DTRACE(O3PipeView)) { 719 inst->decodeTick = curTick() - inst->fetchTick; 720 } |
721#endif 722 723 // Ensure that if it was predicted as a branch, it really is a 724 // branch. 725 if (inst->readPredTaken() && !inst->isControl()) { 726 panic("Instruction predicted as a branch!"); 727 728 ++decodeControlMispred; --- 41 unchanged lines hidden --- |