1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 248 unchanged lines hidden (view full) --- 257 258 return false; 259} 260 261template<class Impl> 262void 263DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) 264{ |
265 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch prediction " 266 "detected at decode.\n", tid, inst->seqNum); |
267 268 // Send back mispredict information. 269 toFetch->decodeInfo[tid].branchMispredict = true; 270 toFetch->decodeInfo[tid].predIncorrect = true; |
271 toFetch->decodeInfo[tid].squash = true; |
272 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; |
273 toFetch->decodeInfo[tid].nextMicroPC = inst->readMicroPC(); |
274 |
275#if ISA_HAS_DELAY_SLOT |
276 toFetch->decodeInfo[tid].nextPC = inst->readPC() + sizeof(TheISA::MachInst); 277 toFetch->decodeInfo[tid].nextNPC = inst->branchTarget(); |
278 toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() != 279 (inst->readNextPC() + sizeof(TheISA::MachInst)); 280#else |
281 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 282 toFetch->decodeInfo[tid].nextNPC = 283 inst->branchTarget() + sizeof(TheISA::MachInst); |
284 toFetch->decodeInfo[tid].branchTaken = 285 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); 286#endif 287 |
288 |
289 InstSeqNum squash_seq_num = inst->seqNum; 290 291 // Might have to tell fetch to unblock. 292 if (decodeStatus[tid] == Blocked || 293 decodeStatus[tid] == Unblocking) { 294 toFetch->decodeUnblock[tid] = 1; 295 } 296 --- 438 unchanged lines hidden (view full) --- 735 736 if (inst->branchTarget() != inst->readPredPC()) { 737 ++decodeBranchMispred; 738 739 // Might want to set some sort of boolean and just do 740 // a check at the end 741 squash(inst, inst->threadNumber); 742 Addr target = inst->branchTarget(); |
743 744#if ISA_HAS_DELAY_SLOT 745 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %#x PredNextPC: %#x\n", 746 inst->seqNum, inst->readPC() + sizeof(TheISA::MachInst), target); 747 |
748 //The micro pc after an instruction level branch should be 0 |
749 inst->setPredTarg(inst->readPC() + sizeof(TheISA::MachInst), target, 0); 750#else 751 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %#x PredNextPC: %#x\n", 752 inst->seqNum, target, target + sizeof(TheISA::MachInst)); 753 //The micro pc after an instruction level branch should be 0 |
754 inst->setPredTarg(target, target + sizeof(TheISA::MachInst), 0); |
755#endif |
756 break; 757 } 758 } 759 } 760 761 // If we didn't process all instructions, then we will need to block 762 // and put all those instructions into the skid buffer. 763 if (!insts_to_decode.empty()) { 764 block(tid); 765 } 766 767 // Record that decode has written to the time buffer for activity 768 // tracking. 769 if (toRenameIndex) { 770 wroteToTimeBuffer = true; 771 } 772} |