265,266c265,266
< DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction "
< "detected at decode.\n", tid);
---
> DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch prediction "
> "detected at decode.\n", tid, inst->seqNum);
271d270
< toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
273,277c272
< toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
< ///FIXME There needs to be a way to set the nextPC and nextNPC
< ///explicitly for ISAs with delay slots.
< toFetch->decodeInfo[tid].nextNPC =
< inst->branchTarget() + sizeof(TheISA::MachInst);
---
> toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
278a274
>
279a276,277
> toFetch->decodeInfo[tid].nextPC = inst->readPC() + sizeof(TheISA::MachInst);
> toFetch->decodeInfo[tid].nextNPC = inst->branchTarget();
282a281,283
> toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
> toFetch->decodeInfo[tid].nextNPC =
> inst->branchTarget() + sizeof(TheISA::MachInst);
286a288
>
740a743,747
>
> #if ISA_HAS_DELAY_SLOT
> DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %#x PredNextPC: %#x\n",
> inst->seqNum, inst->readPC() + sizeof(TheISA::MachInst), target);
>
741a749,753
> inst->setPredTarg(inst->readPC() + sizeof(TheISA::MachInst), target, 0);
> #else
> DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %#x PredNextPC: %#x\n",
> inst->seqNum, target, target + sizeof(TheISA::MachInst));
> //The micro pc after an instruction level branch should be 0
742a755
> #endif