284a285,288
> ///FIXME There needs to be a way to set the nextPC and nextNPC
> ///explicitly for ISAs with delay slots.
> toFetch->decodeInfo[tid].nextNPC =
> inst->branchTarget() + sizeof(TheISA::MachInst);
427,428c431
< std::list<unsigned>::iterator threads = activeThreads->begin();
< std::list<unsigned>::iterator end = activeThreads->end();
---
> std::list<unsigned>::iterator threads = (*activeThreads).begin();
430,432c433,434
< while (threads != end) {
< unsigned tid = *threads++;
< if (!skidBuffer[tid].empty())
---
> while (threads != (*activeThreads).end()) {
> if (!skidBuffer[*threads++].empty())
445,446c447
< std::list<unsigned>::iterator threads = activeThreads->begin();
< std::list<unsigned>::iterator end = activeThreads->end();
---
> std::list<unsigned>::iterator threads = (*activeThreads).begin();
448c449,451
< while (threads != end) {
---
> threads = (*activeThreads).begin();
>
> while (threads != (*activeThreads).end()) {
601,602c604
< std::list<unsigned>::iterator threads = activeThreads->begin();
< std::list<unsigned>::iterator end = activeThreads->end();
---
> std::list<unsigned>::iterator threads = (*activeThreads).begin();
607,608c609,610
< while (threads != end) {
< unsigned tid = *threads++;
---
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
746,748c748,750
< if (inst->predTaken() && !inst->isControl()) {
< DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n",inst->predPC,
< inst->nextPC + 4);
---
> if (inst->readPredTaken() && !inst->isControl()) {
> DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n",
> inst->readPredPC(), inst->readNextPC() + 4);
765c767
< if (inst->branchTarget() != inst->readPredTarg()) {
---
> if (inst->branchTarget() != inst->readPredPC()) {
772c774,775
< inst->setPredTarg(inst->branchTarget());
---
> Addr target = inst->branchTarget();
> inst->setPredTarg(target, target + sizeof(TheISA::MachInst));
778c781
< if (inst->predTaken() && inst->isCondDelaySlot()) {
---
> if (inst->readPredTaken() && inst->isCondDelaySlot()) {
784c787,789
< inst->setPredTarg(inst->branchTarget());
---
> Addr target = inst->branchTarget();
> inst->setPredTarg(target,
> target + sizeof(TheISA::MachInst));
803c808,810
< squashInst[tid]->setPredTarg(squashInst[tid]->branchTarget());
---
> Addr target = squashInst[tid]->branchTarget();
> squashInst[tid]->setPredTarg(target,
> target + sizeof(TheISA::MachInst));