427c427,428
< std::list<unsigned>::iterator threads = (*activeThreads).begin();
---
> std::list<unsigned>::iterator threads = activeThreads->begin();
> std::list<unsigned>::iterator end = activeThreads->end();
429,430c430,432
< while (threads != (*activeThreads).end()) {
< if (!skidBuffer[*threads++].empty())
---
> while (threads != end) {
> unsigned tid = *threads++;
> if (!skidBuffer[tid].empty())
443c445,446
< std::list<unsigned>::iterator threads = (*activeThreads).begin();
---
> std::list<unsigned>::iterator threads = activeThreads->begin();
> std::list<unsigned>::iterator end = activeThreads->end();
445,447c448
< threads = (*activeThreads).begin();
<
< while (threads != (*activeThreads).end()) {
---
> while (threads != end) {
600c601,602
< std::list<unsigned>::iterator threads = (*activeThreads).begin();
---
> std::list<unsigned>::iterator threads = activeThreads->begin();
> std::list<unsigned>::iterator end = activeThreads->end();
605,606c607,608
< while (threads != (*activeThreads).end()) {
< unsigned tid = *threads++;
---
> while (threads != end) {
> unsigned tid = *threads++;
744c746
< if (inst->readPredTaken() && !inst->isControl()) {
---
> if (inst->predTaken() && !inst->isControl()) {
763c765
< if (inst->branchTarget() != inst->readPredPC()) {
---
> if (inst->branchTarget() != inst->readPredTarg()) {
770,771c772
< Addr target = inst->branchTarget();
< inst->setPredTarg(target, target + sizeof(TheISA::MachInst));
---
> inst->setPredTarg(inst->branchTarget());
777c778
< if (inst->readPredTaken() && inst->isCondDelaySlot()) {
---
> if (inst->predTaken() && inst->isCondDelaySlot()) {
783,785c784
< Addr target = inst->branchTarget();
< inst->setPredTarg(target,
< target + sizeof(TheISA::MachInst));
---
> inst->setPredTarg(inst->branchTarget());
804,806c803
< Addr target = squashInst[tid]->branchTarget();
< squashInst[tid]->setPredTarg(target,
< target + sizeof(TheISA::MachInst));
---
> squashInst[tid]->setPredTarg(squashInst[tid]->branchTarget());