1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "arch/types.hh"
32#include "base/trace.hh"
33#include "config/full_system.hh"
34#include "config/the_isa.hh"
35#include "cpu/o3/decode.hh"
36#include "cpu/inst_seq.hh"
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "arch/types.hh"
32#include "base/trace.hh"
33#include "config/full_system.hh"
34#include "config/the_isa.hh"
35#include "cpu/o3/decode.hh"
36#include "cpu/inst_seq.hh"
|
37#include "params/DerivO3CPU.hh"
38
39using namespace std;
40
41template<class Impl>
42DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
43 : cpu(_cpu),
44 renameToDecodeDelay(params->renameToDecodeDelay),
45 iewToDecodeDelay(params->iewToDecodeDelay),
46 commitToDecodeDelay(params->commitToDecodeDelay),
47 fetchToDecodeDelay(params->fetchToDecodeDelay),
48 decodeWidth(params->decodeWidth),
49 numThreads(params->numThreads)
50{
51 _status = Inactive;
52
53 // Setup status, make sure stall signals are clear.
54 for (ThreadID tid = 0; tid < numThreads; ++tid) {
55 decodeStatus[tid] = Idle;
56
57 stalls[tid].rename = false;
58 stalls[tid].iew = false;
59 stalls[tid].commit = false;
60 }
61
62 // @todo: Make into a parameter
63 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth;
64}
65
66template <class Impl>
67std::string
68DefaultDecode<Impl>::name() const
69{
70 return cpu->name() + ".decode";
71}
72
73template <class Impl>
74void
75DefaultDecode<Impl>::regStats()
76{
77 decodeIdleCycles
78 .name(name() + ".DECODE:IdleCycles")
79 .desc("Number of cycles decode is idle")
80 .prereq(decodeIdleCycles);
81 decodeBlockedCycles
82 .name(name() + ".DECODE:BlockedCycles")
83 .desc("Number of cycles decode is blocked")
84 .prereq(decodeBlockedCycles);
85 decodeRunCycles
86 .name(name() + ".DECODE:RunCycles")
87 .desc("Number of cycles decode is running")
88 .prereq(decodeRunCycles);
89 decodeUnblockCycles
90 .name(name() + ".DECODE:UnblockCycles")
91 .desc("Number of cycles decode is unblocking")
92 .prereq(decodeUnblockCycles);
93 decodeSquashCycles
94 .name(name() + ".DECODE:SquashCycles")
95 .desc("Number of cycles decode is squashing")
96 .prereq(decodeSquashCycles);
97 decodeBranchResolved
98 .name(name() + ".DECODE:BranchResolved")
99 .desc("Number of times decode resolved a branch")
100 .prereq(decodeBranchResolved);
101 decodeBranchMispred
102 .name(name() + ".DECODE:BranchMispred")
103 .desc("Number of times decode detected a branch misprediction")
104 .prereq(decodeBranchMispred);
105 decodeControlMispred
106 .name(name() + ".DECODE:ControlMispred")
107 .desc("Number of times decode detected an instruction incorrectly"
108 " predicted as a control")
109 .prereq(decodeControlMispred);
110 decodeDecodedInsts
111 .name(name() + ".DECODE:DecodedInsts")
112 .desc("Number of instructions handled by decode")
113 .prereq(decodeDecodedInsts);
114 decodeSquashedInsts
115 .name(name() + ".DECODE:SquashedInsts")
116 .desc("Number of squashed instructions handled by decode")
117 .prereq(decodeSquashedInsts);
118}
119
120template<class Impl>
121void
122DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
123{
124 timeBuffer = tb_ptr;
125
126 // Setup wire to write information back to fetch.
127 toFetch = timeBuffer->getWire(0);
128
129 // Create wires to get information from proper places in time buffer.
130 fromRename = timeBuffer->getWire(-renameToDecodeDelay);
131 fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
132 fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
133}
134
135template<class Impl>
136void
137DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
138{
139 decodeQueue = dq_ptr;
140
141 // Setup wire to write information to proper place in decode queue.
142 toRename = decodeQueue->getWire(0);
143}
144
145template<class Impl>
146void
147DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
148{
149 fetchQueue = fq_ptr;
150
151 // Setup wire to read information from fetch queue.
152 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
153}
154
155template<class Impl>
156void
157DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
158{
159 activeThreads = at_ptr;
160}
161
162template <class Impl>
163bool
164DefaultDecode<Impl>::drain()
165{
166 // Decode is done draining at any time.
167 cpu->signalDrained();
168 return true;
169}
170
171template <class Impl>
172void
173DefaultDecode<Impl>::takeOverFrom()
174{
175 _status = Inactive;
176
177 // Be sure to reset state and clear out any old instructions.
178 for (ThreadID tid = 0; tid < numThreads; ++tid) {
179 decodeStatus[tid] = Idle;
180
181 stalls[tid].rename = false;
182 stalls[tid].iew = false;
183 stalls[tid].commit = false;
184 while (!insts[tid].empty())
185 insts[tid].pop();
186 while (!skidBuffer[tid].empty())
187 skidBuffer[tid].pop();
188 branchCount[tid] = 0;
189 }
190 wroteToTimeBuffer = false;
191}
192
193template<class Impl>
194bool
195DefaultDecode<Impl>::checkStall(ThreadID tid) const
196{
197 bool ret_val = false;
198
199 if (stalls[tid].rename) {
200 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
201 ret_val = true;
202 } else if (stalls[tid].iew) {
203 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
204 ret_val = true;
205 } else if (stalls[tid].commit) {
206 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
207 ret_val = true;
208 }
209
210 return ret_val;
211}
212
213template<class Impl>
214inline bool
215DefaultDecode<Impl>::fetchInstsValid()
216{
217 return fromFetch->size > 0;
218}
219
220template<class Impl>
221bool
222DefaultDecode<Impl>::block(ThreadID tid)
223{
224 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
225
226 // Add the current inputs to the skid buffer so they can be
227 // reprocessed when this stage unblocks.
228 skidInsert(tid);
229
230 // If the decode status is blocked or unblocking then decode has not yet
231 // signalled fetch to unblock. In that case, there is no need to tell
232 // fetch to block.
233 if (decodeStatus[tid] != Blocked) {
234 // Set the status to Blocked.
235 decodeStatus[tid] = Blocked;
236
237 if (decodeStatus[tid] != Unblocking) {
238 toFetch->decodeBlock[tid] = true;
239 wroteToTimeBuffer = true;
240 }
241
242 return true;
243 }
244
245 return false;
246}
247
248template<class Impl>
249bool
250DefaultDecode<Impl>::unblock(ThreadID tid)
251{
252 // Decode is done unblocking only if the skid buffer is empty.
253 if (skidBuffer[tid].empty()) {
254 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
255 toFetch->decodeUnblock[tid] = true;
256 wroteToTimeBuffer = true;
257
258 decodeStatus[tid] = Running;
259 return true;
260 }
261
262 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
263
264 return false;
265}
266
267template<class Impl>
268void
269DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
270{
271 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch "
272 "prediction detected at decode.\n", tid, inst->seqNum);
273
274 // Send back mispredict information.
275 toFetch->decodeInfo[tid].branchMispredict = true;
276 toFetch->decodeInfo[tid].predIncorrect = true;
277 toFetch->decodeInfo[tid].squash = true;
278 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
279 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
280 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
281
282 InstSeqNum squash_seq_num = inst->seqNum;
283
284 // Might have to tell fetch to unblock.
285 if (decodeStatus[tid] == Blocked ||
286 decodeStatus[tid] == Unblocking) {
287 toFetch->decodeUnblock[tid] = 1;
288 }
289
290 // Set status to squashing.
291 decodeStatus[tid] = Squashing;
292
293 for (int i=0; i<fromFetch->size; i++) {
294 if (fromFetch->insts[i]->threadNumber == tid &&
295 fromFetch->insts[i]->seqNum > squash_seq_num) {
296 fromFetch->insts[i]->setSquashed();
297 }
298 }
299
300 // Clear the instruction list and skid buffer in case they have any
301 // insts in them.
302 while (!insts[tid].empty()) {
303 insts[tid].pop();
304 }
305
306 while (!skidBuffer[tid].empty()) {
307 skidBuffer[tid].pop();
308 }
309
310 // Squash instructions up until this one
311 cpu->removeInstsUntil(squash_seq_num, tid);
312}
313
314template<class Impl>
315unsigned
316DefaultDecode<Impl>::squash(ThreadID tid)
317{
318 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
319
320 if (decodeStatus[tid] == Blocked ||
321 decodeStatus[tid] == Unblocking) {
322#if !FULL_SYSTEM
323 // In syscall emulation, we can have both a block and a squash due
324 // to a syscall in the same cycle. This would cause both signals to
325 // be high. This shouldn't happen in full system.
326 // @todo: Determine if this still happens.
327 if (toFetch->decodeBlock[tid]) {
328 toFetch->decodeBlock[tid] = 0;
329 } else {
330 toFetch->decodeUnblock[tid] = 1;
331 }
332#else
333 toFetch->decodeUnblock[tid] = 1;
334#endif
335 }
336
337 // Set status to squashing.
338 decodeStatus[tid] = Squashing;
339
340 // Go through incoming instructions from fetch and squash them.
341 unsigned squash_count = 0;
342
343 for (int i=0; i<fromFetch->size; i++) {
344 if (fromFetch->insts[i]->threadNumber == tid) {
345 fromFetch->insts[i]->setSquashed();
346 squash_count++;
347 }
348 }
349
350 // Clear the instruction list and skid buffer in case they have any
351 // insts in them.
352 while (!insts[tid].empty()) {
353 insts[tid].pop();
354 }
355
356 while (!skidBuffer[tid].empty()) {
357 skidBuffer[tid].pop();
358 }
359
360 return squash_count;
361}
362
363template<class Impl>
364void
365DefaultDecode<Impl>::skidInsert(ThreadID tid)
366{
367 DynInstPtr inst = NULL;
368
369 while (!insts[tid].empty()) {
370 inst = insts[tid].front();
371
372 insts[tid].pop();
373
374 assert(tid == inst->threadNumber);
375
376 DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n",
377 inst->seqNum, inst->pcState(), inst->threadNumber);
378
379 skidBuffer[tid].push(inst);
380 }
381
382 // @todo: Eventually need to enforce this by not letting a thread
383 // fetch past its skidbuffer
384 assert(skidBuffer[tid].size() <= skidBufferMax);
385}
386
387template<class Impl>
388bool
389DefaultDecode<Impl>::skidsEmpty()
390{
391 list<ThreadID>::iterator threads = activeThreads->begin();
392 list<ThreadID>::iterator end = activeThreads->end();
393
394 while (threads != end) {
395 ThreadID tid = *threads++;
396 if (!skidBuffer[tid].empty())
397 return false;
398 }
399
400 return true;
401}
402
403template<class Impl>
404void
405DefaultDecode<Impl>::updateStatus()
406{
407 bool any_unblocking = false;
408
409 list<ThreadID>::iterator threads = activeThreads->begin();
410 list<ThreadID>::iterator end = activeThreads->end();
411
412 while (threads != end) {
413 ThreadID tid = *threads++;
414
415 if (decodeStatus[tid] == Unblocking) {
416 any_unblocking = true;
417 break;
418 }
419 }
420
421 // Decode will have activity if it's unblocking.
422 if (any_unblocking) {
423 if (_status == Inactive) {
424 _status = Active;
425
426 DPRINTF(Activity, "Activating stage.\n");
427
428 cpu->activateStage(O3CPU::DecodeIdx);
429 }
430 } else {
431 // If it's not unblocking, then decode will not have any internal
432 // activity. Switch it to inactive.
433 if (_status == Active) {
434 _status = Inactive;
435 DPRINTF(Activity, "Deactivating stage.\n");
436
437 cpu->deactivateStage(O3CPU::DecodeIdx);
438 }
439 }
440}
441
442template <class Impl>
443void
444DefaultDecode<Impl>::sortInsts()
445{
446 int insts_from_fetch = fromFetch->size;
447#ifdef DEBUG
448 for (ThreadID tid = 0; tid < numThreads; tid++)
449 assert(insts[tid].empty());
450#endif
451 for (int i = 0; i < insts_from_fetch; ++i) {
452 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
453 }
454}
455
456template<class Impl>
457void
458DefaultDecode<Impl>::readStallSignals(ThreadID tid)
459{
460 if (fromRename->renameBlock[tid]) {
461 stalls[tid].rename = true;
462 }
463
464 if (fromRename->renameUnblock[tid]) {
465 assert(stalls[tid].rename);
466 stalls[tid].rename = false;
467 }
468
469 if (fromIEW->iewBlock[tid]) {
470 stalls[tid].iew = true;
471 }
472
473 if (fromIEW->iewUnblock[tid]) {
474 assert(stalls[tid].iew);
475 stalls[tid].iew = false;
476 }
477
478 if (fromCommit->commitBlock[tid]) {
479 stalls[tid].commit = true;
480 }
481
482 if (fromCommit->commitUnblock[tid]) {
483 assert(stalls[tid].commit);
484 stalls[tid].commit = false;
485 }
486}
487
488template <class Impl>
489bool
490DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid)
491{
492 // Check if there's a squash signal, squash if there is.
493 // Check stall signals, block if necessary.
494 // If status was blocked
495 // Check if stall conditions have passed
496 // if so then go to unblocking
497 // If status was Squashing
498 // check if squashing is not high. Switch to running this cycle.
499
500 // Update the per thread stall statuses.
501 readStallSignals(tid);
502
503 // Check squash signals from commit.
504 if (fromCommit->commitInfo[tid].squash) {
505
506 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
507 "from commit.\n", tid);
508
509 squash(tid);
510
511 return true;
512 }
513
514 // Check ROB squash signals from commit.
515 if (fromCommit->commitInfo[tid].robSquashing) {
516 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
517
518 // Continue to squash.
519 decodeStatus[tid] = Squashing;
520
521 return true;
522 }
523
524 if (checkStall(tid)) {
525 return block(tid);
526 }
527
528 if (decodeStatus[tid] == Blocked) {
529 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
530 tid);
531
532 decodeStatus[tid] = Unblocking;
533
534 unblock(tid);
535
536 return true;
537 }
538
539 if (decodeStatus[tid] == Squashing) {
540 // Switch status to running if decode isn't being told to block or
541 // squash this cycle.
542 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
543 tid);
544
545 decodeStatus[tid] = Running;
546
547 return false;
548 }
549
550 // If we've reached this point, we have not gotten any signals that
551 // cause decode to change its status. Decode remains the same as before.
552 return false;
553}
554
555template<class Impl>
556void
557DefaultDecode<Impl>::tick()
558{
559 wroteToTimeBuffer = false;
560
561 bool status_change = false;
562
563 toRenameIndex = 0;
564
565 list<ThreadID>::iterator threads = activeThreads->begin();
566 list<ThreadID>::iterator end = activeThreads->end();
567
568 sortInsts();
569
570 //Check stall and squash signals.
571 while (threads != end) {
572 ThreadID tid = *threads++;
573
574 DPRINTF(Decode,"Processing [tid:%i]\n",tid);
575 status_change = checkSignalsAndUpdate(tid) || status_change;
576
577 decode(status_change, tid);
578 }
579
580 if (status_change) {
581 updateStatus();
582 }
583
584 if (wroteToTimeBuffer) {
585 DPRINTF(Activity, "Activity this cycle.\n");
586
587 cpu->activityThisCycle();
588 }
589}
590
591template<class Impl>
592void
593DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid)
594{
595 // If status is Running or idle,
596 // call decodeInsts()
597 // If status is Unblocking,
598 // buffer any instructions coming from fetch
599 // continue trying to empty skid buffer
600 // check if stall conditions have passed
601
602 if (decodeStatus[tid] == Blocked) {
603 ++decodeBlockedCycles;
604 } else if (decodeStatus[tid] == Squashing) {
605 ++decodeSquashCycles;
606 }
607
608 // Decode should try to decode as many instructions as its bandwidth
609 // will allow, as long as it is not currently blocked.
610 if (decodeStatus[tid] == Running ||
611 decodeStatus[tid] == Idle) {
612 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
613 "stage.\n",tid);
614
615 decodeInsts(tid);
616 } else if (decodeStatus[tid] == Unblocking) {
617 // Make sure that the skid buffer has something in it if the
618 // status is unblocking.
619 assert(!skidsEmpty());
620
621 // If the status was unblocking, then instructions from the skid
622 // buffer were used. Remove those instructions and handle
623 // the rest of unblocking.
624 decodeInsts(tid);
625
626 if (fetchInstsValid()) {
627 // Add the current inputs to the skid buffer so they can be
628 // reprocessed when this stage unblocks.
629 skidInsert(tid);
630 }
631
632 status_change = unblock(tid) || status_change;
633 }
634}
635
636template <class Impl>
637void
638DefaultDecode<Impl>::decodeInsts(ThreadID tid)
639{
640 // Instructions can come either from the skid buffer or the list of
641 // instructions coming from fetch, depending on decode's status.
642 int insts_available = decodeStatus[tid] == Unblocking ?
643 skidBuffer[tid].size() : insts[tid].size();
644
645 if (insts_available == 0) {
646 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
647 " early.\n",tid);
648 // Should I change the status to idle?
649 ++decodeIdleCycles;
650 return;
651 } else if (decodeStatus[tid] == Unblocking) {
652 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
653 "buffer.\n",tid);
654 ++decodeUnblockCycles;
655 } else if (decodeStatus[tid] == Running) {
656 ++decodeRunCycles;
657 }
658
659 DynInstPtr inst;
660
661 std::queue<DynInstPtr>
662 &insts_to_decode = decodeStatus[tid] == Unblocking ?
663 skidBuffer[tid] : insts[tid];
664
665 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
666
667 while (insts_available > 0 && toRenameIndex < decodeWidth) {
668 assert(!insts_to_decode.empty());
669
670 inst = insts_to_decode.front();
671
672 insts_to_decode.pop();
673
674 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
675 "PC %s\n", tid, inst->seqNum, inst->pcState());
676
677 if (inst->isSquashed()) {
678 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is "
679 "squashed, skipping.\n",
680 tid, inst->seqNum, inst->pcState());
681
682 ++decodeSquashedInsts;
683
684 --insts_available;
685
686 continue;
687 }
688
689 // Also check if instructions have no source registers. Mark
690 // them as ready to issue at any time. Not sure if this check
691 // should exist here or at a later stage; however it doesn't matter
692 // too much for function correctness.
693 if (inst->numSrcRegs() == 0) {
694 inst->setCanIssue();
695 }
696
697 // This current instruction is valid, so add it into the decode
698 // queue. The next instruction may not be valid, so check to
699 // see if branches were predicted correctly.
700 toRename->insts[toRenameIndex] = inst;
701
702 ++(toRename->size);
703 ++toRenameIndex;
704 ++decodeDecodedInsts;
705 --insts_available;
706
707 // Ensure that if it was predicted as a branch, it really is a
708 // branch.
709 if (inst->readPredTaken() && !inst->isControl()) {
710 panic("Instruction predicted as a branch!");
711
712 ++decodeControlMispred;
713
714 // Might want to set some sort of boolean and just do
715 // a check at the end
716 squash(inst, inst->threadNumber);
717
718 break;
719 }
720
721 // Go ahead and compute any PC-relative branches.
722 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
723 ++decodeBranchResolved;
724
725 if (!(inst->branchTarget() == inst->readPredTarg())) {
726 ++decodeBranchMispred;
727
728 // Might want to set some sort of boolean and just do
729 // a check at the end
730 squash(inst, inst->threadNumber);
731 TheISA::PCState target = inst->branchTarget();
732
733 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n",
734 inst->seqNum, target);
735 //The micro pc after an instruction level branch should be 0
736 inst->setPredTarg(target);
737 break;
738 }
739 }
740 }
741
742 // If we didn't process all instructions, then we will need to block
743 // and put all those instructions into the skid buffer.
744 if (!insts_to_decode.empty()) {
745 block(tid);
746 }
747
748 // Record that decode has written to the time buffer for activity
749 // tracking.
750 if (toRenameIndex) {
751 wroteToTimeBuffer = true;
752 }
753}
| 39#include "params/DerivO3CPU.hh"
40
41using namespace std;
42
43template<class Impl>
44DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
45 : cpu(_cpu),
46 renameToDecodeDelay(params->renameToDecodeDelay),
47 iewToDecodeDelay(params->iewToDecodeDelay),
48 commitToDecodeDelay(params->commitToDecodeDelay),
49 fetchToDecodeDelay(params->fetchToDecodeDelay),
50 decodeWidth(params->decodeWidth),
51 numThreads(params->numThreads)
52{
53 _status = Inactive;
54
55 // Setup status, make sure stall signals are clear.
56 for (ThreadID tid = 0; tid < numThreads; ++tid) {
57 decodeStatus[tid] = Idle;
58
59 stalls[tid].rename = false;
60 stalls[tid].iew = false;
61 stalls[tid].commit = false;
62 }
63
64 // @todo: Make into a parameter
65 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth;
66}
67
68template <class Impl>
69std::string
70DefaultDecode<Impl>::name() const
71{
72 return cpu->name() + ".decode";
73}
74
75template <class Impl>
76void
77DefaultDecode<Impl>::regStats()
78{
79 decodeIdleCycles
80 .name(name() + ".DECODE:IdleCycles")
81 .desc("Number of cycles decode is idle")
82 .prereq(decodeIdleCycles);
83 decodeBlockedCycles
84 .name(name() + ".DECODE:BlockedCycles")
85 .desc("Number of cycles decode is blocked")
86 .prereq(decodeBlockedCycles);
87 decodeRunCycles
88 .name(name() + ".DECODE:RunCycles")
89 .desc("Number of cycles decode is running")
90 .prereq(decodeRunCycles);
91 decodeUnblockCycles
92 .name(name() + ".DECODE:UnblockCycles")
93 .desc("Number of cycles decode is unblocking")
94 .prereq(decodeUnblockCycles);
95 decodeSquashCycles
96 .name(name() + ".DECODE:SquashCycles")
97 .desc("Number of cycles decode is squashing")
98 .prereq(decodeSquashCycles);
99 decodeBranchResolved
100 .name(name() + ".DECODE:BranchResolved")
101 .desc("Number of times decode resolved a branch")
102 .prereq(decodeBranchResolved);
103 decodeBranchMispred
104 .name(name() + ".DECODE:BranchMispred")
105 .desc("Number of times decode detected a branch misprediction")
106 .prereq(decodeBranchMispred);
107 decodeControlMispred
108 .name(name() + ".DECODE:ControlMispred")
109 .desc("Number of times decode detected an instruction incorrectly"
110 " predicted as a control")
111 .prereq(decodeControlMispred);
112 decodeDecodedInsts
113 .name(name() + ".DECODE:DecodedInsts")
114 .desc("Number of instructions handled by decode")
115 .prereq(decodeDecodedInsts);
116 decodeSquashedInsts
117 .name(name() + ".DECODE:SquashedInsts")
118 .desc("Number of squashed instructions handled by decode")
119 .prereq(decodeSquashedInsts);
120}
121
122template<class Impl>
123void
124DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
125{
126 timeBuffer = tb_ptr;
127
128 // Setup wire to write information back to fetch.
129 toFetch = timeBuffer->getWire(0);
130
131 // Create wires to get information from proper places in time buffer.
132 fromRename = timeBuffer->getWire(-renameToDecodeDelay);
133 fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
134 fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
135}
136
137template<class Impl>
138void
139DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
140{
141 decodeQueue = dq_ptr;
142
143 // Setup wire to write information to proper place in decode queue.
144 toRename = decodeQueue->getWire(0);
145}
146
147template<class Impl>
148void
149DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
150{
151 fetchQueue = fq_ptr;
152
153 // Setup wire to read information from fetch queue.
154 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
155}
156
157template<class Impl>
158void
159DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
160{
161 activeThreads = at_ptr;
162}
163
164template <class Impl>
165bool
166DefaultDecode<Impl>::drain()
167{
168 // Decode is done draining at any time.
169 cpu->signalDrained();
170 return true;
171}
172
173template <class Impl>
174void
175DefaultDecode<Impl>::takeOverFrom()
176{
177 _status = Inactive;
178
179 // Be sure to reset state and clear out any old instructions.
180 for (ThreadID tid = 0; tid < numThreads; ++tid) {
181 decodeStatus[tid] = Idle;
182
183 stalls[tid].rename = false;
184 stalls[tid].iew = false;
185 stalls[tid].commit = false;
186 while (!insts[tid].empty())
187 insts[tid].pop();
188 while (!skidBuffer[tid].empty())
189 skidBuffer[tid].pop();
190 branchCount[tid] = 0;
191 }
192 wroteToTimeBuffer = false;
193}
194
195template<class Impl>
196bool
197DefaultDecode<Impl>::checkStall(ThreadID tid) const
198{
199 bool ret_val = false;
200
201 if (stalls[tid].rename) {
202 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
203 ret_val = true;
204 } else if (stalls[tid].iew) {
205 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
206 ret_val = true;
207 } else if (stalls[tid].commit) {
208 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
209 ret_val = true;
210 }
211
212 return ret_val;
213}
214
215template<class Impl>
216inline bool
217DefaultDecode<Impl>::fetchInstsValid()
218{
219 return fromFetch->size > 0;
220}
221
222template<class Impl>
223bool
224DefaultDecode<Impl>::block(ThreadID tid)
225{
226 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
227
228 // Add the current inputs to the skid buffer so they can be
229 // reprocessed when this stage unblocks.
230 skidInsert(tid);
231
232 // If the decode status is blocked or unblocking then decode has not yet
233 // signalled fetch to unblock. In that case, there is no need to tell
234 // fetch to block.
235 if (decodeStatus[tid] != Blocked) {
236 // Set the status to Blocked.
237 decodeStatus[tid] = Blocked;
238
239 if (decodeStatus[tid] != Unblocking) {
240 toFetch->decodeBlock[tid] = true;
241 wroteToTimeBuffer = true;
242 }
243
244 return true;
245 }
246
247 return false;
248}
249
250template<class Impl>
251bool
252DefaultDecode<Impl>::unblock(ThreadID tid)
253{
254 // Decode is done unblocking only if the skid buffer is empty.
255 if (skidBuffer[tid].empty()) {
256 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
257 toFetch->decodeUnblock[tid] = true;
258 wroteToTimeBuffer = true;
259
260 decodeStatus[tid] = Running;
261 return true;
262 }
263
264 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
265
266 return false;
267}
268
269template<class Impl>
270void
271DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
272{
273 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch "
274 "prediction detected at decode.\n", tid, inst->seqNum);
275
276 // Send back mispredict information.
277 toFetch->decodeInfo[tid].branchMispredict = true;
278 toFetch->decodeInfo[tid].predIncorrect = true;
279 toFetch->decodeInfo[tid].squash = true;
280 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
281 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
282 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
283
284 InstSeqNum squash_seq_num = inst->seqNum;
285
286 // Might have to tell fetch to unblock.
287 if (decodeStatus[tid] == Blocked ||
288 decodeStatus[tid] == Unblocking) {
289 toFetch->decodeUnblock[tid] = 1;
290 }
291
292 // Set status to squashing.
293 decodeStatus[tid] = Squashing;
294
295 for (int i=0; i<fromFetch->size; i++) {
296 if (fromFetch->insts[i]->threadNumber == tid &&
297 fromFetch->insts[i]->seqNum > squash_seq_num) {
298 fromFetch->insts[i]->setSquashed();
299 }
300 }
301
302 // Clear the instruction list and skid buffer in case they have any
303 // insts in them.
304 while (!insts[tid].empty()) {
305 insts[tid].pop();
306 }
307
308 while (!skidBuffer[tid].empty()) {
309 skidBuffer[tid].pop();
310 }
311
312 // Squash instructions up until this one
313 cpu->removeInstsUntil(squash_seq_num, tid);
314}
315
316template<class Impl>
317unsigned
318DefaultDecode<Impl>::squash(ThreadID tid)
319{
320 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
321
322 if (decodeStatus[tid] == Blocked ||
323 decodeStatus[tid] == Unblocking) {
324#if !FULL_SYSTEM
325 // In syscall emulation, we can have both a block and a squash due
326 // to a syscall in the same cycle. This would cause both signals to
327 // be high. This shouldn't happen in full system.
328 // @todo: Determine if this still happens.
329 if (toFetch->decodeBlock[tid]) {
330 toFetch->decodeBlock[tid] = 0;
331 } else {
332 toFetch->decodeUnblock[tid] = 1;
333 }
334#else
335 toFetch->decodeUnblock[tid] = 1;
336#endif
337 }
338
339 // Set status to squashing.
340 decodeStatus[tid] = Squashing;
341
342 // Go through incoming instructions from fetch and squash them.
343 unsigned squash_count = 0;
344
345 for (int i=0; i<fromFetch->size; i++) {
346 if (fromFetch->insts[i]->threadNumber == tid) {
347 fromFetch->insts[i]->setSquashed();
348 squash_count++;
349 }
350 }
351
352 // Clear the instruction list and skid buffer in case they have any
353 // insts in them.
354 while (!insts[tid].empty()) {
355 insts[tid].pop();
356 }
357
358 while (!skidBuffer[tid].empty()) {
359 skidBuffer[tid].pop();
360 }
361
362 return squash_count;
363}
364
365template<class Impl>
366void
367DefaultDecode<Impl>::skidInsert(ThreadID tid)
368{
369 DynInstPtr inst = NULL;
370
371 while (!insts[tid].empty()) {
372 inst = insts[tid].front();
373
374 insts[tid].pop();
375
376 assert(tid == inst->threadNumber);
377
378 DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n",
379 inst->seqNum, inst->pcState(), inst->threadNumber);
380
381 skidBuffer[tid].push(inst);
382 }
383
384 // @todo: Eventually need to enforce this by not letting a thread
385 // fetch past its skidbuffer
386 assert(skidBuffer[tid].size() <= skidBufferMax);
387}
388
389template<class Impl>
390bool
391DefaultDecode<Impl>::skidsEmpty()
392{
393 list<ThreadID>::iterator threads = activeThreads->begin();
394 list<ThreadID>::iterator end = activeThreads->end();
395
396 while (threads != end) {
397 ThreadID tid = *threads++;
398 if (!skidBuffer[tid].empty())
399 return false;
400 }
401
402 return true;
403}
404
405template<class Impl>
406void
407DefaultDecode<Impl>::updateStatus()
408{
409 bool any_unblocking = false;
410
411 list<ThreadID>::iterator threads = activeThreads->begin();
412 list<ThreadID>::iterator end = activeThreads->end();
413
414 while (threads != end) {
415 ThreadID tid = *threads++;
416
417 if (decodeStatus[tid] == Unblocking) {
418 any_unblocking = true;
419 break;
420 }
421 }
422
423 // Decode will have activity if it's unblocking.
424 if (any_unblocking) {
425 if (_status == Inactive) {
426 _status = Active;
427
428 DPRINTF(Activity, "Activating stage.\n");
429
430 cpu->activateStage(O3CPU::DecodeIdx);
431 }
432 } else {
433 // If it's not unblocking, then decode will not have any internal
434 // activity. Switch it to inactive.
435 if (_status == Active) {
436 _status = Inactive;
437 DPRINTF(Activity, "Deactivating stage.\n");
438
439 cpu->deactivateStage(O3CPU::DecodeIdx);
440 }
441 }
442}
443
444template <class Impl>
445void
446DefaultDecode<Impl>::sortInsts()
447{
448 int insts_from_fetch = fromFetch->size;
449#ifdef DEBUG
450 for (ThreadID tid = 0; tid < numThreads; tid++)
451 assert(insts[tid].empty());
452#endif
453 for (int i = 0; i < insts_from_fetch; ++i) {
454 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
455 }
456}
457
458template<class Impl>
459void
460DefaultDecode<Impl>::readStallSignals(ThreadID tid)
461{
462 if (fromRename->renameBlock[tid]) {
463 stalls[tid].rename = true;
464 }
465
466 if (fromRename->renameUnblock[tid]) {
467 assert(stalls[tid].rename);
468 stalls[tid].rename = false;
469 }
470
471 if (fromIEW->iewBlock[tid]) {
472 stalls[tid].iew = true;
473 }
474
475 if (fromIEW->iewUnblock[tid]) {
476 assert(stalls[tid].iew);
477 stalls[tid].iew = false;
478 }
479
480 if (fromCommit->commitBlock[tid]) {
481 stalls[tid].commit = true;
482 }
483
484 if (fromCommit->commitUnblock[tid]) {
485 assert(stalls[tid].commit);
486 stalls[tid].commit = false;
487 }
488}
489
490template <class Impl>
491bool
492DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid)
493{
494 // Check if there's a squash signal, squash if there is.
495 // Check stall signals, block if necessary.
496 // If status was blocked
497 // Check if stall conditions have passed
498 // if so then go to unblocking
499 // If status was Squashing
500 // check if squashing is not high. Switch to running this cycle.
501
502 // Update the per thread stall statuses.
503 readStallSignals(tid);
504
505 // Check squash signals from commit.
506 if (fromCommit->commitInfo[tid].squash) {
507
508 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
509 "from commit.\n", tid);
510
511 squash(tid);
512
513 return true;
514 }
515
516 // Check ROB squash signals from commit.
517 if (fromCommit->commitInfo[tid].robSquashing) {
518 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
519
520 // Continue to squash.
521 decodeStatus[tid] = Squashing;
522
523 return true;
524 }
525
526 if (checkStall(tid)) {
527 return block(tid);
528 }
529
530 if (decodeStatus[tid] == Blocked) {
531 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
532 tid);
533
534 decodeStatus[tid] = Unblocking;
535
536 unblock(tid);
537
538 return true;
539 }
540
541 if (decodeStatus[tid] == Squashing) {
542 // Switch status to running if decode isn't being told to block or
543 // squash this cycle.
544 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
545 tid);
546
547 decodeStatus[tid] = Running;
548
549 return false;
550 }
551
552 // If we've reached this point, we have not gotten any signals that
553 // cause decode to change its status. Decode remains the same as before.
554 return false;
555}
556
557template<class Impl>
558void
559DefaultDecode<Impl>::tick()
560{
561 wroteToTimeBuffer = false;
562
563 bool status_change = false;
564
565 toRenameIndex = 0;
566
567 list<ThreadID>::iterator threads = activeThreads->begin();
568 list<ThreadID>::iterator end = activeThreads->end();
569
570 sortInsts();
571
572 //Check stall and squash signals.
573 while (threads != end) {
574 ThreadID tid = *threads++;
575
576 DPRINTF(Decode,"Processing [tid:%i]\n",tid);
577 status_change = checkSignalsAndUpdate(tid) || status_change;
578
579 decode(status_change, tid);
580 }
581
582 if (status_change) {
583 updateStatus();
584 }
585
586 if (wroteToTimeBuffer) {
587 DPRINTF(Activity, "Activity this cycle.\n");
588
589 cpu->activityThisCycle();
590 }
591}
592
593template<class Impl>
594void
595DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid)
596{
597 // If status is Running or idle,
598 // call decodeInsts()
599 // If status is Unblocking,
600 // buffer any instructions coming from fetch
601 // continue trying to empty skid buffer
602 // check if stall conditions have passed
603
604 if (decodeStatus[tid] == Blocked) {
605 ++decodeBlockedCycles;
606 } else if (decodeStatus[tid] == Squashing) {
607 ++decodeSquashCycles;
608 }
609
610 // Decode should try to decode as many instructions as its bandwidth
611 // will allow, as long as it is not currently blocked.
612 if (decodeStatus[tid] == Running ||
613 decodeStatus[tid] == Idle) {
614 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
615 "stage.\n",tid);
616
617 decodeInsts(tid);
618 } else if (decodeStatus[tid] == Unblocking) {
619 // Make sure that the skid buffer has something in it if the
620 // status is unblocking.
621 assert(!skidsEmpty());
622
623 // If the status was unblocking, then instructions from the skid
624 // buffer were used. Remove those instructions and handle
625 // the rest of unblocking.
626 decodeInsts(tid);
627
628 if (fetchInstsValid()) {
629 // Add the current inputs to the skid buffer so they can be
630 // reprocessed when this stage unblocks.
631 skidInsert(tid);
632 }
633
634 status_change = unblock(tid) || status_change;
635 }
636}
637
638template <class Impl>
639void
640DefaultDecode<Impl>::decodeInsts(ThreadID tid)
641{
642 // Instructions can come either from the skid buffer or the list of
643 // instructions coming from fetch, depending on decode's status.
644 int insts_available = decodeStatus[tid] == Unblocking ?
645 skidBuffer[tid].size() : insts[tid].size();
646
647 if (insts_available == 0) {
648 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
649 " early.\n",tid);
650 // Should I change the status to idle?
651 ++decodeIdleCycles;
652 return;
653 } else if (decodeStatus[tid] == Unblocking) {
654 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
655 "buffer.\n",tid);
656 ++decodeUnblockCycles;
657 } else if (decodeStatus[tid] == Running) {
658 ++decodeRunCycles;
659 }
660
661 DynInstPtr inst;
662
663 std::queue<DynInstPtr>
664 &insts_to_decode = decodeStatus[tid] == Unblocking ?
665 skidBuffer[tid] : insts[tid];
666
667 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
668
669 while (insts_available > 0 && toRenameIndex < decodeWidth) {
670 assert(!insts_to_decode.empty());
671
672 inst = insts_to_decode.front();
673
674 insts_to_decode.pop();
675
676 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
677 "PC %s\n", tid, inst->seqNum, inst->pcState());
678
679 if (inst->isSquashed()) {
680 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is "
681 "squashed, skipping.\n",
682 tid, inst->seqNum, inst->pcState());
683
684 ++decodeSquashedInsts;
685
686 --insts_available;
687
688 continue;
689 }
690
691 // Also check if instructions have no source registers. Mark
692 // them as ready to issue at any time. Not sure if this check
693 // should exist here or at a later stage; however it doesn't matter
694 // too much for function correctness.
695 if (inst->numSrcRegs() == 0) {
696 inst->setCanIssue();
697 }
698
699 // This current instruction is valid, so add it into the decode
700 // queue. The next instruction may not be valid, so check to
701 // see if branches were predicted correctly.
702 toRename->insts[toRenameIndex] = inst;
703
704 ++(toRename->size);
705 ++toRenameIndex;
706 ++decodeDecodedInsts;
707 --insts_available;
708
709 // Ensure that if it was predicted as a branch, it really is a
710 // branch.
711 if (inst->readPredTaken() && !inst->isControl()) {
712 panic("Instruction predicted as a branch!");
713
714 ++decodeControlMispred;
715
716 // Might want to set some sort of boolean and just do
717 // a check at the end
718 squash(inst, inst->threadNumber);
719
720 break;
721 }
722
723 // Go ahead and compute any PC-relative branches.
724 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
725 ++decodeBranchResolved;
726
727 if (!(inst->branchTarget() == inst->readPredTarg())) {
728 ++decodeBranchMispred;
729
730 // Might want to set some sort of boolean and just do
731 // a check at the end
732 squash(inst, inst->threadNumber);
733 TheISA::PCState target = inst->branchTarget();
734
735 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n",
736 inst->seqNum, target);
737 //The micro pc after an instruction level branch should be 0
738 inst->setPredTarg(target);
739 break;
740 }
741 }
742 }
743
744 // If we didn't process all instructions, then we will need to block
745 // and put all those instructions into the skid buffer.
746 if (!insts_to_decode.empty()) {
747 block(tid);
748 }
749
750 // Record that decode has written to the time buffer for activity
751 // tracking.
752 if (toRenameIndex) {
753 wroteToTimeBuffer = true;
754 }
755}
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