1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "cpu/o3/decode.hh" 32 33template<class Impl> 34DefaultDecode<Impl>::DefaultDecode(Params *params) 35 : renameToDecodeDelay(params->renameToDecodeDelay), 36 iewToDecodeDelay(params->iewToDecodeDelay), 37 commitToDecodeDelay(params->commitToDecodeDelay), 38 fetchToDecodeDelay(params->fetchToDecodeDelay), 39 decodeWidth(params->decodeWidth), 40 numThreads(params->numberOfThreads) 41{ 42 _status = Inactive; 43 44 // Setup status, make sure stall signals are clear. 45 for (int i = 0; i < numThreads; ++i) { 46 decodeStatus[i] = Idle; 47 48 stalls[i].rename = false; 49 stalls[i].iew = false; 50 stalls[i].commit = false; 51 52 squashAfterDelaySlot[i] = false; 53 } 54 55 // @todo: Make into a parameter 56 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 57} 58 59template <class Impl> 60std::string 61DefaultDecode<Impl>::name() const 62{ 63 return cpu->name() + ".decode"; 64} 65 66template <class Impl> 67void 68DefaultDecode<Impl>::regStats() 69{ 70 decodeIdleCycles 71 .name(name() + ".DECODE:IdleCycles") 72 .desc("Number of cycles decode is idle") 73 .prereq(decodeIdleCycles); 74 decodeBlockedCycles 75 .name(name() + ".DECODE:BlockedCycles") 76 .desc("Number of cycles decode is blocked") 77 .prereq(decodeBlockedCycles); 78 decodeRunCycles 79 .name(name() + ".DECODE:RunCycles") 80 .desc("Number of cycles decode is running") 81 .prereq(decodeRunCycles); 82 decodeUnblockCycles 83 .name(name() + ".DECODE:UnblockCycles") 84 .desc("Number of cycles decode is unblocking") 85 .prereq(decodeUnblockCycles); 86 decodeSquashCycles 87 .name(name() + ".DECODE:SquashCycles") 88 .desc("Number of cycles decode is squashing") 89 .prereq(decodeSquashCycles); 90 decodeBranchResolved 91 .name(name() + ".DECODE:BranchResolved") 92 .desc("Number of times decode resolved a branch") 93 .prereq(decodeBranchResolved); 94 decodeBranchMispred 95 .name(name() + ".DECODE:BranchMispred") 96 .desc("Number of times decode detected a branch misprediction") 97 .prereq(decodeBranchMispred); 98 decodeControlMispred 99 .name(name() + ".DECODE:ControlMispred") 100 .desc("Number of times decode detected an instruction incorrectly" 101 " predicted as a control") 102 .prereq(decodeControlMispred); 103 decodeDecodedInsts 104 .name(name() + ".DECODE:DecodedInsts") 105 .desc("Number of instructions handled by decode") 106 .prereq(decodeDecodedInsts); 107 decodeSquashedInsts 108 .name(name() + ".DECODE:SquashedInsts") 109 .desc("Number of squashed instructions handled by decode") 110 .prereq(decodeSquashedInsts); 111} 112 113template<class Impl> 114void 115DefaultDecode<Impl>::setCPU(O3CPU *cpu_ptr) 116{
| 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "cpu/o3/decode.hh" 32 33template<class Impl> 34DefaultDecode<Impl>::DefaultDecode(Params *params) 35 : renameToDecodeDelay(params->renameToDecodeDelay), 36 iewToDecodeDelay(params->iewToDecodeDelay), 37 commitToDecodeDelay(params->commitToDecodeDelay), 38 fetchToDecodeDelay(params->fetchToDecodeDelay), 39 decodeWidth(params->decodeWidth), 40 numThreads(params->numberOfThreads) 41{ 42 _status = Inactive; 43 44 // Setup status, make sure stall signals are clear. 45 for (int i = 0; i < numThreads; ++i) { 46 decodeStatus[i] = Idle; 47 48 stalls[i].rename = false; 49 stalls[i].iew = false; 50 stalls[i].commit = false; 51 52 squashAfterDelaySlot[i] = false; 53 } 54 55 // @todo: Make into a parameter 56 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 57} 58 59template <class Impl> 60std::string 61DefaultDecode<Impl>::name() const 62{ 63 return cpu->name() + ".decode"; 64} 65 66template <class Impl> 67void 68DefaultDecode<Impl>::regStats() 69{ 70 decodeIdleCycles 71 .name(name() + ".DECODE:IdleCycles") 72 .desc("Number of cycles decode is idle") 73 .prereq(decodeIdleCycles); 74 decodeBlockedCycles 75 .name(name() + ".DECODE:BlockedCycles") 76 .desc("Number of cycles decode is blocked") 77 .prereq(decodeBlockedCycles); 78 decodeRunCycles 79 .name(name() + ".DECODE:RunCycles") 80 .desc("Number of cycles decode is running") 81 .prereq(decodeRunCycles); 82 decodeUnblockCycles 83 .name(name() + ".DECODE:UnblockCycles") 84 .desc("Number of cycles decode is unblocking") 85 .prereq(decodeUnblockCycles); 86 decodeSquashCycles 87 .name(name() + ".DECODE:SquashCycles") 88 .desc("Number of cycles decode is squashing") 89 .prereq(decodeSquashCycles); 90 decodeBranchResolved 91 .name(name() + ".DECODE:BranchResolved") 92 .desc("Number of times decode resolved a branch") 93 .prereq(decodeBranchResolved); 94 decodeBranchMispred 95 .name(name() + ".DECODE:BranchMispred") 96 .desc("Number of times decode detected a branch misprediction") 97 .prereq(decodeBranchMispred); 98 decodeControlMispred 99 .name(name() + ".DECODE:ControlMispred") 100 .desc("Number of times decode detected an instruction incorrectly" 101 " predicted as a control") 102 .prereq(decodeControlMispred); 103 decodeDecodedInsts 104 .name(name() + ".DECODE:DecodedInsts") 105 .desc("Number of instructions handled by decode") 106 .prereq(decodeDecodedInsts); 107 decodeSquashedInsts 108 .name(name() + ".DECODE:SquashedInsts") 109 .desc("Number of squashed instructions handled by decode") 110 .prereq(decodeSquashedInsts); 111} 112 113template<class Impl> 114void 115DefaultDecode<Impl>::setCPU(O3CPU *cpu_ptr) 116{
|
164 activeThreads = at_ptr; 165} 166 167template <class Impl> 168bool 169DefaultDecode<Impl>::drain() 170{ 171 // Decode is done draining at any time. 172 cpu->signalDrained(); 173 return true; 174} 175 176template <class Impl> 177void 178DefaultDecode<Impl>::takeOverFrom() 179{ 180 _status = Inactive; 181 182 // Be sure to reset state and clear out any old instructions. 183 for (int i = 0; i < numThreads; ++i) { 184 decodeStatus[i] = Idle; 185 186 stalls[i].rename = false; 187 stalls[i].iew = false; 188 stalls[i].commit = false; 189 while (!insts[i].empty()) 190 insts[i].pop(); 191 while (!skidBuffer[i].empty()) 192 skidBuffer[i].pop(); 193 branchCount[i] = 0; 194 } 195 wroteToTimeBuffer = false; 196} 197 198template<class Impl> 199bool 200DefaultDecode<Impl>::checkStall(unsigned tid) const 201{ 202 bool ret_val = false; 203 204 if (stalls[tid].rename) { 205 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 206 ret_val = true; 207 } else if (stalls[tid].iew) { 208 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 209 ret_val = true; 210 } else if (stalls[tid].commit) { 211 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 212 ret_val = true; 213 } 214 215 return ret_val; 216} 217 218template<class Impl> 219inline bool 220DefaultDecode<Impl>::fetchInstsValid() 221{ 222 return fromFetch->size > 0; 223} 224 225template<class Impl> 226bool 227DefaultDecode<Impl>::block(unsigned tid) 228{ 229 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 230 231 // Add the current inputs to the skid buffer so they can be 232 // reprocessed when this stage unblocks. 233 skidInsert(tid); 234 235 // If the decode status is blocked or unblocking then decode has not yet 236 // signalled fetch to unblock. In that case, there is no need to tell 237 // fetch to block. 238 if (decodeStatus[tid] != Blocked) { 239 // Set the status to Blocked. 240 decodeStatus[tid] = Blocked; 241 242 if (decodeStatus[tid] != Unblocking) { 243 toFetch->decodeBlock[tid] = true; 244 wroteToTimeBuffer = true; 245 } 246 247 return true; 248 } 249 250 return false; 251} 252 253template<class Impl> 254bool 255DefaultDecode<Impl>::unblock(unsigned tid) 256{ 257 // Decode is done unblocking only if the skid buffer is empty. 258 if (skidBuffer[tid].empty()) { 259 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 260 toFetch->decodeUnblock[tid] = true; 261 wroteToTimeBuffer = true; 262 263 decodeStatus[tid] = Running; 264 return true; 265 } 266 267 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 268 269 return false; 270} 271 272template<class Impl> 273void 274DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) 275{ 276 DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction " 277 "detected at decode.\n", tid); 278 279 // Send back mispredict information. 280 toFetch->decodeInfo[tid].branchMispredict = true; 281 toFetch->decodeInfo[tid].predIncorrect = true; 282 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 283 toFetch->decodeInfo[tid].squash = true; 284 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 285 ///FIXME There needs to be a way to set the nextPC and nextNPC 286 ///explicitly for ISAs with delay slots. 287 toFetch->decodeInfo[tid].nextNPC = 288 inst->branchTarget() + sizeof(TheISA::MachInst); 289#if ISA_HAS_DELAY_SLOT 290 toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() != 291 (inst->readNextPC() + sizeof(TheISA::MachInst)); 292 293 toFetch->decodeInfo[tid].bdelayDoneSeqNum = bdelayDoneSeqNum[tid]; 294 squashAfterDelaySlot[tid] = false; 295 296 InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid]; 297#else 298 toFetch->decodeInfo[tid].branchTaken = 299 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); 300 301 InstSeqNum squash_seq_num = inst->seqNum; 302#endif 303 304 // Might have to tell fetch to unblock. 305 if (decodeStatus[tid] == Blocked || 306 decodeStatus[tid] == Unblocking) { 307 toFetch->decodeUnblock[tid] = 1; 308 } 309 310 // Set status to squashing. 311 decodeStatus[tid] = Squashing; 312 313 for (int i=0; i<fromFetch->size; i++) { 314 if (fromFetch->insts[i]->threadNumber == tid && 315 fromFetch->insts[i]->seqNum > squash_seq_num) { 316 fromFetch->insts[i]->setSquashed(); 317 } 318 } 319 320 // Clear the instruction list and skid buffer in case they have any 321 // insts in them. 322 while (!insts[tid].empty()) { 323 324#if ISA_HAS_DELAY_SLOT 325 if (insts[tid].front()->seqNum <= squash_seq_num) { 326 DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode " 327 "instructions before delay slot [sn:%i]. %i insts" 328 "left in decode.\n", tid, squash_seq_num, 329 insts[tid].size()); 330 break; 331 } 332#endif 333 insts[tid].pop(); 334 } 335 336 while (!skidBuffer[tid].empty()) { 337 338#if ISA_HAS_DELAY_SLOT 339 if (skidBuffer[tid].front()->seqNum <= squash_seq_num) { 340 DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer " 341 "instructions before delay slot [sn:%i]. %i insts" 342 "left in decode.\n", tid, squash_seq_num, 343 insts[tid].size()); 344 break; 345 } 346#endif 347 skidBuffer[tid].pop(); 348 } 349 350 // Squash instructions up until this one 351 cpu->removeInstsUntil(squash_seq_num, tid); 352} 353 354template<class Impl> 355unsigned 356DefaultDecode<Impl>::squash(unsigned tid) 357{ 358 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 359 360 if (decodeStatus[tid] == Blocked || 361 decodeStatus[tid] == Unblocking) { 362#if !FULL_SYSTEM 363 // In syscall emulation, we can have both a block and a squash due 364 // to a syscall in the same cycle. This would cause both signals to 365 // be high. This shouldn't happen in full system. 366 // @todo: Determine if this still happens. 367 if (toFetch->decodeBlock[tid]) { 368 toFetch->decodeBlock[tid] = 0; 369 } else { 370 toFetch->decodeUnblock[tid] = 1; 371 } 372#else 373 toFetch->decodeUnblock[tid] = 1; 374#endif 375 } 376 377 // Set status to squashing. 378 decodeStatus[tid] = Squashing; 379 380 // Go through incoming instructions from fetch and squash them. 381 unsigned squash_count = 0; 382 383 for (int i=0; i<fromFetch->size; i++) { 384 if (fromFetch->insts[i]->threadNumber == tid) { 385 fromFetch->insts[i]->setSquashed(); 386 squash_count++; 387 } 388 } 389 390 // Clear the instruction list and skid buffer in case they have any 391 // insts in them. 392 while (!insts[tid].empty()) { 393 insts[tid].pop(); 394 } 395 396 while (!skidBuffer[tid].empty()) { 397 skidBuffer[tid].pop(); 398 } 399 400 return squash_count; 401} 402 403template<class Impl> 404void 405DefaultDecode<Impl>::skidInsert(unsigned tid) 406{ 407 DynInstPtr inst = NULL; 408 409 while (!insts[tid].empty()) { 410 inst = insts[tid].front(); 411 412 insts[tid].pop(); 413 414 assert(tid == inst->threadNumber); 415 416 DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n", 417 inst->seqNum, inst->readPC(), inst->threadNumber); 418 419 skidBuffer[tid].push(inst); 420 } 421 422 // @todo: Eventually need to enforce this by not letting a thread 423 // fetch past its skidbuffer 424 assert(skidBuffer[tid].size() <= skidBufferMax); 425} 426 427template<class Impl> 428bool 429DefaultDecode<Impl>::skidsEmpty() 430{ 431 std::list<unsigned>::iterator threads = activeThreads->begin(); 432 std::list<unsigned>::iterator end = activeThreads->end(); 433 434 while (threads != end) { 435 unsigned tid = *threads++; 436 if (!skidBuffer[tid].empty()) 437 return false; 438 } 439 440 return true; 441} 442 443template<class Impl> 444void 445DefaultDecode<Impl>::updateStatus() 446{ 447 bool any_unblocking = false; 448 449 std::list<unsigned>::iterator threads = activeThreads->begin(); 450 std::list<unsigned>::iterator end = activeThreads->end(); 451 452 while (threads != end) { 453 unsigned tid = *threads++; 454 455 if (decodeStatus[tid] == Unblocking) { 456 any_unblocking = true; 457 break; 458 } 459 } 460 461 // Decode will have activity if it's unblocking. 462 if (any_unblocking) { 463 if (_status == Inactive) { 464 _status = Active; 465 466 DPRINTF(Activity, "Activating stage.\n"); 467 468 cpu->activateStage(O3CPU::DecodeIdx); 469 } 470 } else { 471 // If it's not unblocking, then decode will not have any internal 472 // activity. Switch it to inactive. 473 if (_status == Active) { 474 _status = Inactive; 475 DPRINTF(Activity, "Deactivating stage.\n"); 476 477 cpu->deactivateStage(O3CPU::DecodeIdx); 478 } 479 } 480} 481 482template <class Impl> 483void 484DefaultDecode<Impl>::sortInsts() 485{ 486 int insts_from_fetch = fromFetch->size; 487#ifdef DEBUG 488 for (int i=0; i < numThreads; i++) 489 assert(insts[i].empty()); 490#endif 491 for (int i = 0; i < insts_from_fetch; ++i) { 492 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 493 } 494} 495 496template<class Impl> 497void 498DefaultDecode<Impl>::readStallSignals(unsigned tid) 499{ 500 if (fromRename->renameBlock[tid]) { 501 stalls[tid].rename = true; 502 } 503 504 if (fromRename->renameUnblock[tid]) { 505 assert(stalls[tid].rename); 506 stalls[tid].rename = false; 507 } 508 509 if (fromIEW->iewBlock[tid]) { 510 stalls[tid].iew = true; 511 } 512 513 if (fromIEW->iewUnblock[tid]) { 514 assert(stalls[tid].iew); 515 stalls[tid].iew = false; 516 } 517 518 if (fromCommit->commitBlock[tid]) { 519 stalls[tid].commit = true; 520 } 521 522 if (fromCommit->commitUnblock[tid]) { 523 assert(stalls[tid].commit); 524 stalls[tid].commit = false; 525 } 526} 527 528template <class Impl> 529bool 530DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid) 531{ 532 // Check if there's a squash signal, squash if there is. 533 // Check stall signals, block if necessary. 534 // If status was blocked 535 // Check if stall conditions have passed 536 // if so then go to unblocking 537 // If status was Squashing 538 // check if squashing is not high. Switch to running this cycle. 539 540 // Update the per thread stall statuses. 541 readStallSignals(tid); 542 543 // Check squash signals from commit. 544 if (fromCommit->commitInfo[tid].squash) { 545 546 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 547 "from commit.\n", tid); 548 549 squash(tid); 550 551 return true; 552 } 553 554 // Check ROB squash signals from commit. 555 if (fromCommit->commitInfo[tid].robSquashing) { 556 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 557 558 // Continue to squash. 559 decodeStatus[tid] = Squashing; 560 561 return true; 562 } 563 564 if (checkStall(tid)) { 565 return block(tid); 566 } 567 568 if (decodeStatus[tid] == Blocked) { 569 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 570 tid); 571 572 decodeStatus[tid] = Unblocking; 573 574 unblock(tid); 575 576 return true; 577 } 578 579 if (decodeStatus[tid] == Squashing) { 580 // Switch status to running if decode isn't being told to block or 581 // squash this cycle. 582 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 583 tid); 584 585 decodeStatus[tid] = Running; 586 587 return false; 588 } 589 590 // If we've reached this point, we have not gotten any signals that 591 // cause decode to change its status. Decode remains the same as before. 592 return false; 593} 594 595template<class Impl> 596void 597DefaultDecode<Impl>::tick() 598{ 599 wroteToTimeBuffer = false; 600 601 bool status_change = false; 602 603 toRenameIndex = 0; 604 605 std::list<unsigned>::iterator threads = activeThreads->begin(); 606 std::list<unsigned>::iterator end = activeThreads->end(); 607 608 sortInsts(); 609 610 //Check stall and squash signals. 611 while (threads != end) { 612 unsigned tid = *threads++; 613 614 DPRINTF(Decode,"Processing [tid:%i]\n",tid); 615 status_change = checkSignalsAndUpdate(tid) || status_change; 616 617 decode(status_change, tid); 618 } 619 620 if (status_change) { 621 updateStatus(); 622 } 623 624 if (wroteToTimeBuffer) { 625 DPRINTF(Activity, "Activity this cycle.\n"); 626 627 cpu->activityThisCycle(); 628 } 629} 630 631template<class Impl> 632void 633DefaultDecode<Impl>::decode(bool &status_change, unsigned tid) 634{ 635 // If status is Running or idle, 636 // call decodeInsts() 637 // If status is Unblocking, 638 // buffer any instructions coming from fetch 639 // continue trying to empty skid buffer 640 // check if stall conditions have passed 641 642 if (decodeStatus[tid] == Blocked) { 643 ++decodeBlockedCycles; 644 } else if (decodeStatus[tid] == Squashing) { 645 ++decodeSquashCycles; 646 } 647 648 // Decode should try to decode as many instructions as its bandwidth 649 // will allow, as long as it is not currently blocked. 650 if (decodeStatus[tid] == Running || 651 decodeStatus[tid] == Idle) { 652 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 653 "stage.\n",tid); 654 655 decodeInsts(tid); 656 } else if (decodeStatus[tid] == Unblocking) { 657 // Make sure that the skid buffer has something in it if the 658 // status is unblocking. 659 assert(!skidsEmpty()); 660 661 // If the status was unblocking, then instructions from the skid 662 // buffer were used. Remove those instructions and handle 663 // the rest of unblocking. 664 decodeInsts(tid); 665 666 if (fetchInstsValid()) { 667 // Add the current inputs to the skid buffer so they can be 668 // reprocessed when this stage unblocks. 669 skidInsert(tid); 670 } 671 672 status_change = unblock(tid) || status_change; 673 } 674} 675 676template <class Impl> 677void 678DefaultDecode<Impl>::decodeInsts(unsigned tid) 679{ 680 // Instructions can come either from the skid buffer or the list of 681 // instructions coming from fetch, depending on decode's status. 682 int insts_available = decodeStatus[tid] == Unblocking ? 683 skidBuffer[tid].size() : insts[tid].size(); 684 685 if (insts_available == 0) { 686 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 687 " early.\n",tid); 688 // Should I change the status to idle? 689 ++decodeIdleCycles; 690 return; 691 } else if (decodeStatus[tid] == Unblocking) { 692 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 693 "buffer.\n",tid); 694 ++decodeUnblockCycles; 695 } else if (decodeStatus[tid] == Running) { 696 ++decodeRunCycles; 697 } 698 699 DynInstPtr inst; 700 701 std::queue<DynInstPtr> 702 &insts_to_decode = decodeStatus[tid] == Unblocking ? 703 skidBuffer[tid] : insts[tid]; 704 705 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 706 707 while (insts_available > 0 && toRenameIndex < decodeWidth) { 708 assert(!insts_to_decode.empty()); 709 710 inst = insts_to_decode.front(); 711 712 insts_to_decode.pop(); 713 714 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 715 "PC %#x\n", 716 tid, inst->seqNum, inst->readPC()); 717 718 if (inst->isSquashed()) { 719 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is " 720 "squashed, skipping.\n", 721 tid, inst->seqNum, inst->readPC()); 722 723 ++decodeSquashedInsts; 724 725 --insts_available; 726 727 continue; 728 } 729 730 // Also check if instructions have no source registers. Mark 731 // them as ready to issue at any time. Not sure if this check 732 // should exist here or at a later stage; however it doesn't matter 733 // too much for function correctness. 734 if (inst->numSrcRegs() == 0) { 735 inst->setCanIssue(); 736 } 737 738 // This current instruction is valid, so add it into the decode 739 // queue. The next instruction may not be valid, so check to 740 // see if branches were predicted correctly. 741 toRename->insts[toRenameIndex] = inst; 742 743 ++(toRename->size); 744 ++toRenameIndex; 745 ++decodeDecodedInsts; 746 --insts_available; 747 748 // Ensure that if it was predicted as a branch, it really is a 749 // branch. 750 if (inst->readPredTaken() && !inst->isControl()) { 751 DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n", 752 inst->readPredPC(), inst->readNextPC() + 4); 753 754 panic("Instruction predicted as a branch!"); 755 756 ++decodeControlMispred; 757 758 // Might want to set some sort of boolean and just do 759 // a check at the end 760 squash(inst, inst->threadNumber); 761 762 break; 763 } 764 765 // Go ahead and compute any PC-relative branches. 766 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 767 ++decodeBranchResolved; 768 769 if (inst->branchTarget() != inst->readPredPC()) { 770 ++decodeBranchMispred; 771 772 // Might want to set some sort of boolean and just do 773 // a check at the end 774#if !ISA_HAS_DELAY_SLOT 775 squash(inst, inst->threadNumber); 776 Addr target = inst->branchTarget(); 777 inst->setPredTarg(target, target + sizeof(TheISA::MachInst)); 778 break; 779#else 780 // If mispredicted as taken, then ignore delay slot 781 // instruction... else keep delay slot and squash 782 // after it is sent to rename 783 if (inst->readPredTaken() && inst->isCondDelaySlot()) { 784 DPRINTF(Decode, "[tid:%i]: Conditional delay slot inst." 785 "[sn:%i] PC %#x mispredicted as taken.\n", tid, 786 inst->seqNum, inst->PC); 787 bdelayDoneSeqNum[tid] = inst->seqNum; 788 squash(inst, inst->threadNumber); 789 Addr target = inst->branchTarget(); 790 inst->setPredTarg(target, 791 target + sizeof(TheISA::MachInst)); 792 break; 793 } else { 794 DPRINTF(Decode, "[tid:%i]: Misprediction detected at " 795 "[sn:%i] PC %#x, will squash after delay slot " 796 "inst. is sent to Rename\n", 797 tid, inst->seqNum, inst->PC); 798 bdelayDoneSeqNum[tid] = inst->seqNum + 1; 799 squashAfterDelaySlot[tid] = true; 800 squashInst[tid] = inst; 801 continue; 802 } 803#endif 804 } 805 } 806 807 if (squashAfterDelaySlot[tid]) { 808 assert(!inst->isSquashed()); 809 squash(squashInst[tid], squashInst[tid]->threadNumber); 810 Addr target = squashInst[tid]->branchTarget(); 811 squashInst[tid]->setPredTarg(target, 812 target + sizeof(TheISA::MachInst)); 813 assert(!inst->isSquashed()); 814 break; 815 } 816 } 817 818 // If we didn't process all instructions, then we will need to block 819 // and put all those instructions into the skid buffer. 820 if (!insts_to_decode.empty()) { 821 block(tid); 822 } 823 824 // Record that decode has written to the time buffer for activity 825 // tracking. 826 if (toRenameIndex) { 827 wroteToTimeBuffer = true; 828 } 829}
| 160 activeThreads = at_ptr; 161} 162 163template <class Impl> 164bool 165DefaultDecode<Impl>::drain() 166{ 167 // Decode is done draining at any time. 168 cpu->signalDrained(); 169 return true; 170} 171 172template <class Impl> 173void 174DefaultDecode<Impl>::takeOverFrom() 175{ 176 _status = Inactive; 177 178 // Be sure to reset state and clear out any old instructions. 179 for (int i = 0; i < numThreads; ++i) { 180 decodeStatus[i] = Idle; 181 182 stalls[i].rename = false; 183 stalls[i].iew = false; 184 stalls[i].commit = false; 185 while (!insts[i].empty()) 186 insts[i].pop(); 187 while (!skidBuffer[i].empty()) 188 skidBuffer[i].pop(); 189 branchCount[i] = 0; 190 } 191 wroteToTimeBuffer = false; 192} 193 194template<class Impl> 195bool 196DefaultDecode<Impl>::checkStall(unsigned tid) const 197{ 198 bool ret_val = false; 199 200 if (stalls[tid].rename) { 201 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 202 ret_val = true; 203 } else if (stalls[tid].iew) { 204 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 205 ret_val = true; 206 } else if (stalls[tid].commit) { 207 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 208 ret_val = true; 209 } 210 211 return ret_val; 212} 213 214template<class Impl> 215inline bool 216DefaultDecode<Impl>::fetchInstsValid() 217{ 218 return fromFetch->size > 0; 219} 220 221template<class Impl> 222bool 223DefaultDecode<Impl>::block(unsigned tid) 224{ 225 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 226 227 // Add the current inputs to the skid buffer so they can be 228 // reprocessed when this stage unblocks. 229 skidInsert(tid); 230 231 // If the decode status is blocked or unblocking then decode has not yet 232 // signalled fetch to unblock. In that case, there is no need to tell 233 // fetch to block. 234 if (decodeStatus[tid] != Blocked) { 235 // Set the status to Blocked. 236 decodeStatus[tid] = Blocked; 237 238 if (decodeStatus[tid] != Unblocking) { 239 toFetch->decodeBlock[tid] = true; 240 wroteToTimeBuffer = true; 241 } 242 243 return true; 244 } 245 246 return false; 247} 248 249template<class Impl> 250bool 251DefaultDecode<Impl>::unblock(unsigned tid) 252{ 253 // Decode is done unblocking only if the skid buffer is empty. 254 if (skidBuffer[tid].empty()) { 255 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 256 toFetch->decodeUnblock[tid] = true; 257 wroteToTimeBuffer = true; 258 259 decodeStatus[tid] = Running; 260 return true; 261 } 262 263 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 264 265 return false; 266} 267 268template<class Impl> 269void 270DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) 271{ 272 DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction " 273 "detected at decode.\n", tid); 274 275 // Send back mispredict information. 276 toFetch->decodeInfo[tid].branchMispredict = true; 277 toFetch->decodeInfo[tid].predIncorrect = true; 278 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 279 toFetch->decodeInfo[tid].squash = true; 280 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 281 ///FIXME There needs to be a way to set the nextPC and nextNPC 282 ///explicitly for ISAs with delay slots. 283 toFetch->decodeInfo[tid].nextNPC = 284 inst->branchTarget() + sizeof(TheISA::MachInst); 285#if ISA_HAS_DELAY_SLOT 286 toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() != 287 (inst->readNextPC() + sizeof(TheISA::MachInst)); 288 289 toFetch->decodeInfo[tid].bdelayDoneSeqNum = bdelayDoneSeqNum[tid]; 290 squashAfterDelaySlot[tid] = false; 291 292 InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid]; 293#else 294 toFetch->decodeInfo[tid].branchTaken = 295 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); 296 297 InstSeqNum squash_seq_num = inst->seqNum; 298#endif 299 300 // Might have to tell fetch to unblock. 301 if (decodeStatus[tid] == Blocked || 302 decodeStatus[tid] == Unblocking) { 303 toFetch->decodeUnblock[tid] = 1; 304 } 305 306 // Set status to squashing. 307 decodeStatus[tid] = Squashing; 308 309 for (int i=0; i<fromFetch->size; i++) { 310 if (fromFetch->insts[i]->threadNumber == tid && 311 fromFetch->insts[i]->seqNum > squash_seq_num) { 312 fromFetch->insts[i]->setSquashed(); 313 } 314 } 315 316 // Clear the instruction list and skid buffer in case they have any 317 // insts in them. 318 while (!insts[tid].empty()) { 319 320#if ISA_HAS_DELAY_SLOT 321 if (insts[tid].front()->seqNum <= squash_seq_num) { 322 DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode " 323 "instructions before delay slot [sn:%i]. %i insts" 324 "left in decode.\n", tid, squash_seq_num, 325 insts[tid].size()); 326 break; 327 } 328#endif 329 insts[tid].pop(); 330 } 331 332 while (!skidBuffer[tid].empty()) { 333 334#if ISA_HAS_DELAY_SLOT 335 if (skidBuffer[tid].front()->seqNum <= squash_seq_num) { 336 DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer " 337 "instructions before delay slot [sn:%i]. %i insts" 338 "left in decode.\n", tid, squash_seq_num, 339 insts[tid].size()); 340 break; 341 } 342#endif 343 skidBuffer[tid].pop(); 344 } 345 346 // Squash instructions up until this one 347 cpu->removeInstsUntil(squash_seq_num, tid); 348} 349 350template<class Impl> 351unsigned 352DefaultDecode<Impl>::squash(unsigned tid) 353{ 354 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 355 356 if (decodeStatus[tid] == Blocked || 357 decodeStatus[tid] == Unblocking) { 358#if !FULL_SYSTEM 359 // In syscall emulation, we can have both a block and a squash due 360 // to a syscall in the same cycle. This would cause both signals to 361 // be high. This shouldn't happen in full system. 362 // @todo: Determine if this still happens. 363 if (toFetch->decodeBlock[tid]) { 364 toFetch->decodeBlock[tid] = 0; 365 } else { 366 toFetch->decodeUnblock[tid] = 1; 367 } 368#else 369 toFetch->decodeUnblock[tid] = 1; 370#endif 371 } 372 373 // Set status to squashing. 374 decodeStatus[tid] = Squashing; 375 376 // Go through incoming instructions from fetch and squash them. 377 unsigned squash_count = 0; 378 379 for (int i=0; i<fromFetch->size; i++) { 380 if (fromFetch->insts[i]->threadNumber == tid) { 381 fromFetch->insts[i]->setSquashed(); 382 squash_count++; 383 } 384 } 385 386 // Clear the instruction list and skid buffer in case they have any 387 // insts in them. 388 while (!insts[tid].empty()) { 389 insts[tid].pop(); 390 } 391 392 while (!skidBuffer[tid].empty()) { 393 skidBuffer[tid].pop(); 394 } 395 396 return squash_count; 397} 398 399template<class Impl> 400void 401DefaultDecode<Impl>::skidInsert(unsigned tid) 402{ 403 DynInstPtr inst = NULL; 404 405 while (!insts[tid].empty()) { 406 inst = insts[tid].front(); 407 408 insts[tid].pop(); 409 410 assert(tid == inst->threadNumber); 411 412 DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n", 413 inst->seqNum, inst->readPC(), inst->threadNumber); 414 415 skidBuffer[tid].push(inst); 416 } 417 418 // @todo: Eventually need to enforce this by not letting a thread 419 // fetch past its skidbuffer 420 assert(skidBuffer[tid].size() <= skidBufferMax); 421} 422 423template<class Impl> 424bool 425DefaultDecode<Impl>::skidsEmpty() 426{ 427 std::list<unsigned>::iterator threads = activeThreads->begin(); 428 std::list<unsigned>::iterator end = activeThreads->end(); 429 430 while (threads != end) { 431 unsigned tid = *threads++; 432 if (!skidBuffer[tid].empty()) 433 return false; 434 } 435 436 return true; 437} 438 439template<class Impl> 440void 441DefaultDecode<Impl>::updateStatus() 442{ 443 bool any_unblocking = false; 444 445 std::list<unsigned>::iterator threads = activeThreads->begin(); 446 std::list<unsigned>::iterator end = activeThreads->end(); 447 448 while (threads != end) { 449 unsigned tid = *threads++; 450 451 if (decodeStatus[tid] == Unblocking) { 452 any_unblocking = true; 453 break; 454 } 455 } 456 457 // Decode will have activity if it's unblocking. 458 if (any_unblocking) { 459 if (_status == Inactive) { 460 _status = Active; 461 462 DPRINTF(Activity, "Activating stage.\n"); 463 464 cpu->activateStage(O3CPU::DecodeIdx); 465 } 466 } else { 467 // If it's not unblocking, then decode will not have any internal 468 // activity. Switch it to inactive. 469 if (_status == Active) { 470 _status = Inactive; 471 DPRINTF(Activity, "Deactivating stage.\n"); 472 473 cpu->deactivateStage(O3CPU::DecodeIdx); 474 } 475 } 476} 477 478template <class Impl> 479void 480DefaultDecode<Impl>::sortInsts() 481{ 482 int insts_from_fetch = fromFetch->size; 483#ifdef DEBUG 484 for (int i=0; i < numThreads; i++) 485 assert(insts[i].empty()); 486#endif 487 for (int i = 0; i < insts_from_fetch; ++i) { 488 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 489 } 490} 491 492template<class Impl> 493void 494DefaultDecode<Impl>::readStallSignals(unsigned tid) 495{ 496 if (fromRename->renameBlock[tid]) { 497 stalls[tid].rename = true; 498 } 499 500 if (fromRename->renameUnblock[tid]) { 501 assert(stalls[tid].rename); 502 stalls[tid].rename = false; 503 } 504 505 if (fromIEW->iewBlock[tid]) { 506 stalls[tid].iew = true; 507 } 508 509 if (fromIEW->iewUnblock[tid]) { 510 assert(stalls[tid].iew); 511 stalls[tid].iew = false; 512 } 513 514 if (fromCommit->commitBlock[tid]) { 515 stalls[tid].commit = true; 516 } 517 518 if (fromCommit->commitUnblock[tid]) { 519 assert(stalls[tid].commit); 520 stalls[tid].commit = false; 521 } 522} 523 524template <class Impl> 525bool 526DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid) 527{ 528 // Check if there's a squash signal, squash if there is. 529 // Check stall signals, block if necessary. 530 // If status was blocked 531 // Check if stall conditions have passed 532 // if so then go to unblocking 533 // If status was Squashing 534 // check if squashing is not high. Switch to running this cycle. 535 536 // Update the per thread stall statuses. 537 readStallSignals(tid); 538 539 // Check squash signals from commit. 540 if (fromCommit->commitInfo[tid].squash) { 541 542 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 543 "from commit.\n", tid); 544 545 squash(tid); 546 547 return true; 548 } 549 550 // Check ROB squash signals from commit. 551 if (fromCommit->commitInfo[tid].robSquashing) { 552 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 553 554 // Continue to squash. 555 decodeStatus[tid] = Squashing; 556 557 return true; 558 } 559 560 if (checkStall(tid)) { 561 return block(tid); 562 } 563 564 if (decodeStatus[tid] == Blocked) { 565 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 566 tid); 567 568 decodeStatus[tid] = Unblocking; 569 570 unblock(tid); 571 572 return true; 573 } 574 575 if (decodeStatus[tid] == Squashing) { 576 // Switch status to running if decode isn't being told to block or 577 // squash this cycle. 578 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 579 tid); 580 581 decodeStatus[tid] = Running; 582 583 return false; 584 } 585 586 // If we've reached this point, we have not gotten any signals that 587 // cause decode to change its status. Decode remains the same as before. 588 return false; 589} 590 591template<class Impl> 592void 593DefaultDecode<Impl>::tick() 594{ 595 wroteToTimeBuffer = false; 596 597 bool status_change = false; 598 599 toRenameIndex = 0; 600 601 std::list<unsigned>::iterator threads = activeThreads->begin(); 602 std::list<unsigned>::iterator end = activeThreads->end(); 603 604 sortInsts(); 605 606 //Check stall and squash signals. 607 while (threads != end) { 608 unsigned tid = *threads++; 609 610 DPRINTF(Decode,"Processing [tid:%i]\n",tid); 611 status_change = checkSignalsAndUpdate(tid) || status_change; 612 613 decode(status_change, tid); 614 } 615 616 if (status_change) { 617 updateStatus(); 618 } 619 620 if (wroteToTimeBuffer) { 621 DPRINTF(Activity, "Activity this cycle.\n"); 622 623 cpu->activityThisCycle(); 624 } 625} 626 627template<class Impl> 628void 629DefaultDecode<Impl>::decode(bool &status_change, unsigned tid) 630{ 631 // If status is Running or idle, 632 // call decodeInsts() 633 // If status is Unblocking, 634 // buffer any instructions coming from fetch 635 // continue trying to empty skid buffer 636 // check if stall conditions have passed 637 638 if (decodeStatus[tid] == Blocked) { 639 ++decodeBlockedCycles; 640 } else if (decodeStatus[tid] == Squashing) { 641 ++decodeSquashCycles; 642 } 643 644 // Decode should try to decode as many instructions as its bandwidth 645 // will allow, as long as it is not currently blocked. 646 if (decodeStatus[tid] == Running || 647 decodeStatus[tid] == Idle) { 648 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 649 "stage.\n",tid); 650 651 decodeInsts(tid); 652 } else if (decodeStatus[tid] == Unblocking) { 653 // Make sure that the skid buffer has something in it if the 654 // status is unblocking. 655 assert(!skidsEmpty()); 656 657 // If the status was unblocking, then instructions from the skid 658 // buffer were used. Remove those instructions and handle 659 // the rest of unblocking. 660 decodeInsts(tid); 661 662 if (fetchInstsValid()) { 663 // Add the current inputs to the skid buffer so they can be 664 // reprocessed when this stage unblocks. 665 skidInsert(tid); 666 } 667 668 status_change = unblock(tid) || status_change; 669 } 670} 671 672template <class Impl> 673void 674DefaultDecode<Impl>::decodeInsts(unsigned tid) 675{ 676 // Instructions can come either from the skid buffer or the list of 677 // instructions coming from fetch, depending on decode's status. 678 int insts_available = decodeStatus[tid] == Unblocking ? 679 skidBuffer[tid].size() : insts[tid].size(); 680 681 if (insts_available == 0) { 682 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 683 " early.\n",tid); 684 // Should I change the status to idle? 685 ++decodeIdleCycles; 686 return; 687 } else if (decodeStatus[tid] == Unblocking) { 688 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 689 "buffer.\n",tid); 690 ++decodeUnblockCycles; 691 } else if (decodeStatus[tid] == Running) { 692 ++decodeRunCycles; 693 } 694 695 DynInstPtr inst; 696 697 std::queue<DynInstPtr> 698 &insts_to_decode = decodeStatus[tid] == Unblocking ? 699 skidBuffer[tid] : insts[tid]; 700 701 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 702 703 while (insts_available > 0 && toRenameIndex < decodeWidth) { 704 assert(!insts_to_decode.empty()); 705 706 inst = insts_to_decode.front(); 707 708 insts_to_decode.pop(); 709 710 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 711 "PC %#x\n", 712 tid, inst->seqNum, inst->readPC()); 713 714 if (inst->isSquashed()) { 715 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is " 716 "squashed, skipping.\n", 717 tid, inst->seqNum, inst->readPC()); 718 719 ++decodeSquashedInsts; 720 721 --insts_available; 722 723 continue; 724 } 725 726 // Also check if instructions have no source registers. Mark 727 // them as ready to issue at any time. Not sure if this check 728 // should exist here or at a later stage; however it doesn't matter 729 // too much for function correctness. 730 if (inst->numSrcRegs() == 0) { 731 inst->setCanIssue(); 732 } 733 734 // This current instruction is valid, so add it into the decode 735 // queue. The next instruction may not be valid, so check to 736 // see if branches were predicted correctly. 737 toRename->insts[toRenameIndex] = inst; 738 739 ++(toRename->size); 740 ++toRenameIndex; 741 ++decodeDecodedInsts; 742 --insts_available; 743 744 // Ensure that if it was predicted as a branch, it really is a 745 // branch. 746 if (inst->readPredTaken() && !inst->isControl()) { 747 DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n", 748 inst->readPredPC(), inst->readNextPC() + 4); 749 750 panic("Instruction predicted as a branch!"); 751 752 ++decodeControlMispred; 753 754 // Might want to set some sort of boolean and just do 755 // a check at the end 756 squash(inst, inst->threadNumber); 757 758 break; 759 } 760 761 // Go ahead and compute any PC-relative branches. 762 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 763 ++decodeBranchResolved; 764 765 if (inst->branchTarget() != inst->readPredPC()) { 766 ++decodeBranchMispred; 767 768 // Might want to set some sort of boolean and just do 769 // a check at the end 770#if !ISA_HAS_DELAY_SLOT 771 squash(inst, inst->threadNumber); 772 Addr target = inst->branchTarget(); 773 inst->setPredTarg(target, target + sizeof(TheISA::MachInst)); 774 break; 775#else 776 // If mispredicted as taken, then ignore delay slot 777 // instruction... else keep delay slot and squash 778 // after it is sent to rename 779 if (inst->readPredTaken() && inst->isCondDelaySlot()) { 780 DPRINTF(Decode, "[tid:%i]: Conditional delay slot inst." 781 "[sn:%i] PC %#x mispredicted as taken.\n", tid, 782 inst->seqNum, inst->PC); 783 bdelayDoneSeqNum[tid] = inst->seqNum; 784 squash(inst, inst->threadNumber); 785 Addr target = inst->branchTarget(); 786 inst->setPredTarg(target, 787 target + sizeof(TheISA::MachInst)); 788 break; 789 } else { 790 DPRINTF(Decode, "[tid:%i]: Misprediction detected at " 791 "[sn:%i] PC %#x, will squash after delay slot " 792 "inst. is sent to Rename\n", 793 tid, inst->seqNum, inst->PC); 794 bdelayDoneSeqNum[tid] = inst->seqNum + 1; 795 squashAfterDelaySlot[tid] = true; 796 squashInst[tid] = inst; 797 continue; 798 } 799#endif 800 } 801 } 802 803 if (squashAfterDelaySlot[tid]) { 804 assert(!inst->isSquashed()); 805 squash(squashInst[tid], squashInst[tid]->threadNumber); 806 Addr target = squashInst[tid]->branchTarget(); 807 squashInst[tid]->setPredTarg(target, 808 target + sizeof(TheISA::MachInst)); 809 assert(!inst->isSquashed()); 810 break; 811 } 812 } 813 814 // If we didn't process all instructions, then we will need to block 815 // and put all those instructions into the skid buffer. 816 if (!insts_to_decode.empty()) { 817 block(tid); 818 } 819 820 // Record that decode has written to the time buffer for activity 821 // tracking. 822 if (toRenameIndex) { 823 wroteToTimeBuffer = true; 824 } 825}
|