1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "cpu/o3/decode.hh"
32
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "cpu/o3/decode.hh"
32
|
33using namespace std;
34
| |
35template<class Impl>
36DefaultDecode<Impl>::DefaultDecode(Params *params)
37 : renameToDecodeDelay(params->renameToDecodeDelay),
38 iewToDecodeDelay(params->iewToDecodeDelay),
39 commitToDecodeDelay(params->commitToDecodeDelay),
40 fetchToDecodeDelay(params->fetchToDecodeDelay),
41 decodeWidth(params->decodeWidth),
42 numThreads(params->numberOfThreads)
43{
44 _status = Inactive;
45
46 // Setup status, make sure stall signals are clear.
47 for (int i = 0; i < numThreads; ++i) {
48 decodeStatus[i] = Idle;
49
50 stalls[i].rename = false;
51 stalls[i].iew = false;
52 stalls[i].commit = false;
53
54 squashAfterDelaySlot[i] = false;
55 }
56
57 // @todo: Make into a parameter
58 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth;
59}
60
61template <class Impl>
62std::string
63DefaultDecode<Impl>::name() const
64{
65 return cpu->name() + ".decode";
66}
67
68template <class Impl>
69void
70DefaultDecode<Impl>::regStats()
71{
72 decodeIdleCycles
73 .name(name() + ".DECODE:IdleCycles")
74 .desc("Number of cycles decode is idle")
75 .prereq(decodeIdleCycles);
76 decodeBlockedCycles
77 .name(name() + ".DECODE:BlockedCycles")
78 .desc("Number of cycles decode is blocked")
79 .prereq(decodeBlockedCycles);
80 decodeRunCycles
81 .name(name() + ".DECODE:RunCycles")
82 .desc("Number of cycles decode is running")
83 .prereq(decodeRunCycles);
84 decodeUnblockCycles
85 .name(name() + ".DECODE:UnblockCycles")
86 .desc("Number of cycles decode is unblocking")
87 .prereq(decodeUnblockCycles);
88 decodeSquashCycles
89 .name(name() + ".DECODE:SquashCycles")
90 .desc("Number of cycles decode is squashing")
91 .prereq(decodeSquashCycles);
92 decodeBranchResolved
93 .name(name() + ".DECODE:BranchResolved")
94 .desc("Number of times decode resolved a branch")
95 .prereq(decodeBranchResolved);
96 decodeBranchMispred
97 .name(name() + ".DECODE:BranchMispred")
98 .desc("Number of times decode detected a branch misprediction")
99 .prereq(decodeBranchMispred);
100 decodeControlMispred
101 .name(name() + ".DECODE:ControlMispred")
102 .desc("Number of times decode detected an instruction incorrectly"
103 " predicted as a control")
104 .prereq(decodeControlMispred);
105 decodeDecodedInsts
106 .name(name() + ".DECODE:DecodedInsts")
107 .desc("Number of instructions handled by decode")
108 .prereq(decodeDecodedInsts);
109 decodeSquashedInsts
110 .name(name() + ".DECODE:SquashedInsts")
111 .desc("Number of squashed instructions handled by decode")
112 .prereq(decodeSquashedInsts);
113}
114
115template<class Impl>
116void
117DefaultDecode<Impl>::setCPU(O3CPU *cpu_ptr)
118{
119 DPRINTF(Decode, "Setting CPU pointer.\n");
120 cpu = cpu_ptr;
121}
122
123template<class Impl>
124void
125DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
126{
127 DPRINTF(Decode, "Setting time buffer pointer.\n");
128 timeBuffer = tb_ptr;
129
130 // Setup wire to write information back to fetch.
131 toFetch = timeBuffer->getWire(0);
132
133 // Create wires to get information from proper places in time buffer.
134 fromRename = timeBuffer->getWire(-renameToDecodeDelay);
135 fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
136 fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
137}
138
139template<class Impl>
140void
141DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
142{
143 DPRINTF(Decode, "Setting decode queue pointer.\n");
144 decodeQueue = dq_ptr;
145
146 // Setup wire to write information to proper place in decode queue.
147 toRename = decodeQueue->getWire(0);
148}
149
150template<class Impl>
151void
152DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
153{
154 DPRINTF(Decode, "Setting fetch queue pointer.\n");
155 fetchQueue = fq_ptr;
156
157 // Setup wire to read information from fetch queue.
158 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
159}
160
161template<class Impl>
162void
| 33template<class Impl>
34DefaultDecode<Impl>::DefaultDecode(Params *params)
35 : renameToDecodeDelay(params->renameToDecodeDelay),
36 iewToDecodeDelay(params->iewToDecodeDelay),
37 commitToDecodeDelay(params->commitToDecodeDelay),
38 fetchToDecodeDelay(params->fetchToDecodeDelay),
39 decodeWidth(params->decodeWidth),
40 numThreads(params->numberOfThreads)
41{
42 _status = Inactive;
43
44 // Setup status, make sure stall signals are clear.
45 for (int i = 0; i < numThreads; ++i) {
46 decodeStatus[i] = Idle;
47
48 stalls[i].rename = false;
49 stalls[i].iew = false;
50 stalls[i].commit = false;
51
52 squashAfterDelaySlot[i] = false;
53 }
54
55 // @todo: Make into a parameter
56 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth;
57}
58
59template <class Impl>
60std::string
61DefaultDecode<Impl>::name() const
62{
63 return cpu->name() + ".decode";
64}
65
66template <class Impl>
67void
68DefaultDecode<Impl>::regStats()
69{
70 decodeIdleCycles
71 .name(name() + ".DECODE:IdleCycles")
72 .desc("Number of cycles decode is idle")
73 .prereq(decodeIdleCycles);
74 decodeBlockedCycles
75 .name(name() + ".DECODE:BlockedCycles")
76 .desc("Number of cycles decode is blocked")
77 .prereq(decodeBlockedCycles);
78 decodeRunCycles
79 .name(name() + ".DECODE:RunCycles")
80 .desc("Number of cycles decode is running")
81 .prereq(decodeRunCycles);
82 decodeUnblockCycles
83 .name(name() + ".DECODE:UnblockCycles")
84 .desc("Number of cycles decode is unblocking")
85 .prereq(decodeUnblockCycles);
86 decodeSquashCycles
87 .name(name() + ".DECODE:SquashCycles")
88 .desc("Number of cycles decode is squashing")
89 .prereq(decodeSquashCycles);
90 decodeBranchResolved
91 .name(name() + ".DECODE:BranchResolved")
92 .desc("Number of times decode resolved a branch")
93 .prereq(decodeBranchResolved);
94 decodeBranchMispred
95 .name(name() + ".DECODE:BranchMispred")
96 .desc("Number of times decode detected a branch misprediction")
97 .prereq(decodeBranchMispred);
98 decodeControlMispred
99 .name(name() + ".DECODE:ControlMispred")
100 .desc("Number of times decode detected an instruction incorrectly"
101 " predicted as a control")
102 .prereq(decodeControlMispred);
103 decodeDecodedInsts
104 .name(name() + ".DECODE:DecodedInsts")
105 .desc("Number of instructions handled by decode")
106 .prereq(decodeDecodedInsts);
107 decodeSquashedInsts
108 .name(name() + ".DECODE:SquashedInsts")
109 .desc("Number of squashed instructions handled by decode")
110 .prereq(decodeSquashedInsts);
111}
112
113template<class Impl>
114void
115DefaultDecode<Impl>::setCPU(O3CPU *cpu_ptr)
116{
117 DPRINTF(Decode, "Setting CPU pointer.\n");
118 cpu = cpu_ptr;
119}
120
121template<class Impl>
122void
123DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
124{
125 DPRINTF(Decode, "Setting time buffer pointer.\n");
126 timeBuffer = tb_ptr;
127
128 // Setup wire to write information back to fetch.
129 toFetch = timeBuffer->getWire(0);
130
131 // Create wires to get information from proper places in time buffer.
132 fromRename = timeBuffer->getWire(-renameToDecodeDelay);
133 fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
134 fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
135}
136
137template<class Impl>
138void
139DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
140{
141 DPRINTF(Decode, "Setting decode queue pointer.\n");
142 decodeQueue = dq_ptr;
143
144 // Setup wire to write information to proper place in decode queue.
145 toRename = decodeQueue->getWire(0);
146}
147
148template<class Impl>
149void
150DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
151{
152 DPRINTF(Decode, "Setting fetch queue pointer.\n");
153 fetchQueue = fq_ptr;
154
155 // Setup wire to read information from fetch queue.
156 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
157}
158
159template<class Impl>
160void
|
163DefaultDecode::setActiveThreads(list *at_ptr)
| 161DefaultDecode<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
|
164{
165 DPRINTF(Decode, "Setting active threads list pointer.\n");
166 activeThreads = at_ptr;
167}
168
169template <class Impl>
170bool
171DefaultDecode<Impl>::drain()
172{
173 // Decode is done draining at any time.
174 cpu->signalDrained();
175 return true;
176}
177
178template <class Impl>
179void
180DefaultDecode<Impl>::takeOverFrom()
181{
182 _status = Inactive;
183
184 // Be sure to reset state and clear out any old instructions.
185 for (int i = 0; i < numThreads; ++i) {
186 decodeStatus[i] = Idle;
187
188 stalls[i].rename = false;
189 stalls[i].iew = false;
190 stalls[i].commit = false;
191 while (!insts[i].empty())
192 insts[i].pop();
193 while (!skidBuffer[i].empty())
194 skidBuffer[i].pop();
195 branchCount[i] = 0;
196 }
197 wroteToTimeBuffer = false;
198}
199
200template<class Impl>
201bool
202DefaultDecode<Impl>::checkStall(unsigned tid) const
203{
204 bool ret_val = false;
205
206 if (stalls[tid].rename) {
207 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
208 ret_val = true;
209 } else if (stalls[tid].iew) {
210 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
211 ret_val = true;
212 } else if (stalls[tid].commit) {
213 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
214 ret_val = true;
215 }
216
217 return ret_val;
218}
219
220template<class Impl>
221inline bool
222DefaultDecode<Impl>::fetchInstsValid()
223{
224 return fromFetch->size > 0;
225}
226
227template<class Impl>
228bool
229DefaultDecode<Impl>::block(unsigned tid)
230{
231 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
232
233 // Add the current inputs to the skid buffer so they can be
234 // reprocessed when this stage unblocks.
235 skidInsert(tid);
236
237 // If the decode status is blocked or unblocking then decode has not yet
238 // signalled fetch to unblock. In that case, there is no need to tell
239 // fetch to block.
240 if (decodeStatus[tid] != Blocked) {
241 // Set the status to Blocked.
242 decodeStatus[tid] = Blocked;
243
244 if (decodeStatus[tid] != Unblocking) {
245 toFetch->decodeBlock[tid] = true;
246 wroteToTimeBuffer = true;
247 }
248
249 return true;
250 }
251
252 return false;
253}
254
255template<class Impl>
256bool
257DefaultDecode<Impl>::unblock(unsigned tid)
258{
259 // Decode is done unblocking only if the skid buffer is empty.
260 if (skidBuffer[tid].empty()) {
261 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
262 toFetch->decodeUnblock[tid] = true;
263 wroteToTimeBuffer = true;
264
265 decodeStatus[tid] = Running;
266 return true;
267 }
268
269 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
270
271 return false;
272}
273
274template<class Impl>
275void
276DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
277{
278 DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction "
279 "detected at decode.\n", tid);
280
281 // Send back mispredict information.
282 toFetch->decodeInfo[tid].branchMispredict = true;
283 toFetch->decodeInfo[tid].predIncorrect = true;
284 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
285 toFetch->decodeInfo[tid].squash = true;
286 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
287#if THE_ISA == ALPHA_ISA
288 toFetch->decodeInfo[tid].branchTaken =
289 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
290
291 InstSeqNum squash_seq_num = inst->seqNum;
292#else
293 toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() !=
294 (inst->readNextPC() + sizeof(TheISA::MachInst));
295
296 toFetch->decodeInfo[tid].bdelayDoneSeqNum = bdelayDoneSeqNum[tid];
297 squashAfterDelaySlot[tid] = false;
298
299 InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid];
300#endif
301
302 // Might have to tell fetch to unblock.
303 if (decodeStatus[tid] == Blocked ||
304 decodeStatus[tid] == Unblocking) {
305 toFetch->decodeUnblock[tid] = 1;
306 }
307
308 // Set status to squashing.
309 decodeStatus[tid] = Squashing;
310
311 for (int i=0; i<fromFetch->size; i++) {
312 if (fromFetch->insts[i]->threadNumber == tid &&
313 fromFetch->insts[i]->seqNum > squash_seq_num) {
314 fromFetch->insts[i]->setSquashed();
315 }
316 }
317
318 // Clear the instruction list and skid buffer in case they have any
319 // insts in them.
320 while (!insts[tid].empty()) {
321
322#if THE_ISA != ALPHA_ISA
323 if (insts[tid].front()->seqNum <= squash_seq_num) {
324 DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode "
325 "instructions before delay slot [sn:%i]. %i insts"
326 "left in decode.\n", tid, squash_seq_num,
327 insts[tid].size());
328 break;
329 }
330#endif
331 insts[tid].pop();
332 }
333
334 while (!skidBuffer[tid].empty()) {
335
336#if THE_ISA != ALPHA_ISA
337 if (skidBuffer[tid].front()->seqNum <= squash_seq_num) {
338 DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer "
339 "instructions before delay slot [sn:%i]. %i insts"
340 "left in decode.\n", tid, squash_seq_num,
341 insts[tid].size());
342 break;
343 }
344#endif
345 skidBuffer[tid].pop();
346 }
347
348 // Squash instructions up until this one
349 cpu->removeInstsUntil(squash_seq_num, tid);
350}
351
352template<class Impl>
353unsigned
354DefaultDecode<Impl>::squash(unsigned tid)
355{
356 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
357
358 if (decodeStatus[tid] == Blocked ||
359 decodeStatus[tid] == Unblocking) {
360#if !FULL_SYSTEM
361 // In syscall emulation, we can have both a block and a squash due
362 // to a syscall in the same cycle. This would cause both signals to
363 // be high. This shouldn't happen in full system.
364 // @todo: Determine if this still happens.
365 if (toFetch->decodeBlock[tid]) {
366 toFetch->decodeBlock[tid] = 0;
367 } else {
368 toFetch->decodeUnblock[tid] = 1;
369 }
370#else
371 toFetch->decodeUnblock[tid] = 1;
372#endif
373 }
374
375 // Set status to squashing.
376 decodeStatus[tid] = Squashing;
377
378 // Go through incoming instructions from fetch and squash them.
379 unsigned squash_count = 0;
380
381 for (int i=0; i<fromFetch->size; i++) {
382 if (fromFetch->insts[i]->threadNumber == tid) {
383 fromFetch->insts[i]->setSquashed();
384 squash_count++;
385 }
386 }
387
388 // Clear the instruction list and skid buffer in case they have any
389 // insts in them.
390 while (!insts[tid].empty()) {
391 insts[tid].pop();
392 }
393
394 while (!skidBuffer[tid].empty()) {
395 skidBuffer[tid].pop();
396 }
397
398 return squash_count;
399}
400
401template<class Impl>
402void
403DefaultDecode<Impl>::skidInsert(unsigned tid)
404{
405 DynInstPtr inst = NULL;
406
407 while (!insts[tid].empty()) {
408 inst = insts[tid].front();
409
410 insts[tid].pop();
411
412 assert(tid == inst->threadNumber);
413
414 DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n",
415 inst->seqNum, inst->readPC(), inst->threadNumber);
416
417 skidBuffer[tid].push(inst);
418 }
419
420 // @todo: Eventually need to enforce this by not letting a thread
421 // fetch past its skidbuffer
422 assert(skidBuffer[tid].size() <= skidBufferMax);
423}
424
425template<class Impl>
426bool
427DefaultDecode<Impl>::skidsEmpty()
428{
| 162{
163 DPRINTF(Decode, "Setting active threads list pointer.\n");
164 activeThreads = at_ptr;
165}
166
167template <class Impl>
168bool
169DefaultDecode<Impl>::drain()
170{
171 // Decode is done draining at any time.
172 cpu->signalDrained();
173 return true;
174}
175
176template <class Impl>
177void
178DefaultDecode<Impl>::takeOverFrom()
179{
180 _status = Inactive;
181
182 // Be sure to reset state and clear out any old instructions.
183 for (int i = 0; i < numThreads; ++i) {
184 decodeStatus[i] = Idle;
185
186 stalls[i].rename = false;
187 stalls[i].iew = false;
188 stalls[i].commit = false;
189 while (!insts[i].empty())
190 insts[i].pop();
191 while (!skidBuffer[i].empty())
192 skidBuffer[i].pop();
193 branchCount[i] = 0;
194 }
195 wroteToTimeBuffer = false;
196}
197
198template<class Impl>
199bool
200DefaultDecode<Impl>::checkStall(unsigned tid) const
201{
202 bool ret_val = false;
203
204 if (stalls[tid].rename) {
205 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
206 ret_val = true;
207 } else if (stalls[tid].iew) {
208 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
209 ret_val = true;
210 } else if (stalls[tid].commit) {
211 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
212 ret_val = true;
213 }
214
215 return ret_val;
216}
217
218template<class Impl>
219inline bool
220DefaultDecode<Impl>::fetchInstsValid()
221{
222 return fromFetch->size > 0;
223}
224
225template<class Impl>
226bool
227DefaultDecode<Impl>::block(unsigned tid)
228{
229 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
230
231 // Add the current inputs to the skid buffer so they can be
232 // reprocessed when this stage unblocks.
233 skidInsert(tid);
234
235 // If the decode status is blocked or unblocking then decode has not yet
236 // signalled fetch to unblock. In that case, there is no need to tell
237 // fetch to block.
238 if (decodeStatus[tid] != Blocked) {
239 // Set the status to Blocked.
240 decodeStatus[tid] = Blocked;
241
242 if (decodeStatus[tid] != Unblocking) {
243 toFetch->decodeBlock[tid] = true;
244 wroteToTimeBuffer = true;
245 }
246
247 return true;
248 }
249
250 return false;
251}
252
253template<class Impl>
254bool
255DefaultDecode<Impl>::unblock(unsigned tid)
256{
257 // Decode is done unblocking only if the skid buffer is empty.
258 if (skidBuffer[tid].empty()) {
259 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
260 toFetch->decodeUnblock[tid] = true;
261 wroteToTimeBuffer = true;
262
263 decodeStatus[tid] = Running;
264 return true;
265 }
266
267 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
268
269 return false;
270}
271
272template<class Impl>
273void
274DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
275{
276 DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction "
277 "detected at decode.\n", tid);
278
279 // Send back mispredict information.
280 toFetch->decodeInfo[tid].branchMispredict = true;
281 toFetch->decodeInfo[tid].predIncorrect = true;
282 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
283 toFetch->decodeInfo[tid].squash = true;
284 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
285#if THE_ISA == ALPHA_ISA
286 toFetch->decodeInfo[tid].branchTaken =
287 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
288
289 InstSeqNum squash_seq_num = inst->seqNum;
290#else
291 toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() !=
292 (inst->readNextPC() + sizeof(TheISA::MachInst));
293
294 toFetch->decodeInfo[tid].bdelayDoneSeqNum = bdelayDoneSeqNum[tid];
295 squashAfterDelaySlot[tid] = false;
296
297 InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid];
298#endif
299
300 // Might have to tell fetch to unblock.
301 if (decodeStatus[tid] == Blocked ||
302 decodeStatus[tid] == Unblocking) {
303 toFetch->decodeUnblock[tid] = 1;
304 }
305
306 // Set status to squashing.
307 decodeStatus[tid] = Squashing;
308
309 for (int i=0; i<fromFetch->size; i++) {
310 if (fromFetch->insts[i]->threadNumber == tid &&
311 fromFetch->insts[i]->seqNum > squash_seq_num) {
312 fromFetch->insts[i]->setSquashed();
313 }
314 }
315
316 // Clear the instruction list and skid buffer in case they have any
317 // insts in them.
318 while (!insts[tid].empty()) {
319
320#if THE_ISA != ALPHA_ISA
321 if (insts[tid].front()->seqNum <= squash_seq_num) {
322 DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode "
323 "instructions before delay slot [sn:%i]. %i insts"
324 "left in decode.\n", tid, squash_seq_num,
325 insts[tid].size());
326 break;
327 }
328#endif
329 insts[tid].pop();
330 }
331
332 while (!skidBuffer[tid].empty()) {
333
334#if THE_ISA != ALPHA_ISA
335 if (skidBuffer[tid].front()->seqNum <= squash_seq_num) {
336 DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer "
337 "instructions before delay slot [sn:%i]. %i insts"
338 "left in decode.\n", tid, squash_seq_num,
339 insts[tid].size());
340 break;
341 }
342#endif
343 skidBuffer[tid].pop();
344 }
345
346 // Squash instructions up until this one
347 cpu->removeInstsUntil(squash_seq_num, tid);
348}
349
350template<class Impl>
351unsigned
352DefaultDecode<Impl>::squash(unsigned tid)
353{
354 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
355
356 if (decodeStatus[tid] == Blocked ||
357 decodeStatus[tid] == Unblocking) {
358#if !FULL_SYSTEM
359 // In syscall emulation, we can have both a block and a squash due
360 // to a syscall in the same cycle. This would cause both signals to
361 // be high. This shouldn't happen in full system.
362 // @todo: Determine if this still happens.
363 if (toFetch->decodeBlock[tid]) {
364 toFetch->decodeBlock[tid] = 0;
365 } else {
366 toFetch->decodeUnblock[tid] = 1;
367 }
368#else
369 toFetch->decodeUnblock[tid] = 1;
370#endif
371 }
372
373 // Set status to squashing.
374 decodeStatus[tid] = Squashing;
375
376 // Go through incoming instructions from fetch and squash them.
377 unsigned squash_count = 0;
378
379 for (int i=0; i<fromFetch->size; i++) {
380 if (fromFetch->insts[i]->threadNumber == tid) {
381 fromFetch->insts[i]->setSquashed();
382 squash_count++;
383 }
384 }
385
386 // Clear the instruction list and skid buffer in case they have any
387 // insts in them.
388 while (!insts[tid].empty()) {
389 insts[tid].pop();
390 }
391
392 while (!skidBuffer[tid].empty()) {
393 skidBuffer[tid].pop();
394 }
395
396 return squash_count;
397}
398
399template<class Impl>
400void
401DefaultDecode<Impl>::skidInsert(unsigned tid)
402{
403 DynInstPtr inst = NULL;
404
405 while (!insts[tid].empty()) {
406 inst = insts[tid].front();
407
408 insts[tid].pop();
409
410 assert(tid == inst->threadNumber);
411
412 DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n",
413 inst->seqNum, inst->readPC(), inst->threadNumber);
414
415 skidBuffer[tid].push(inst);
416 }
417
418 // @todo: Eventually need to enforce this by not letting a thread
419 // fetch past its skidbuffer
420 assert(skidBuffer[tid].size() <= skidBufferMax);
421}
422
423template<class Impl>
424bool
425DefaultDecode<Impl>::skidsEmpty()
426{
|
429 list::iterator threads = (*activeThreads).begin();
| 427 std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
430
431 while (threads != (*activeThreads).end()) {
432 if (!skidBuffer[*threads++].empty())
433 return false;
434 }
435
436 return true;
437}
438
439template<class Impl>
440void
441DefaultDecode<Impl>::updateStatus()
442{
443 bool any_unblocking = false;
444
| 428
429 while (threads != (*activeThreads).end()) {
430 if (!skidBuffer[*threads++].empty())
431 return false;
432 }
433
434 return true;
435}
436
437template<class Impl>
438void
439DefaultDecode<Impl>::updateStatus()
440{
441 bool any_unblocking = false;
442
|
445 list::iterator threads = (*activeThreads).begin();
| 443 std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
446
447 threads = (*activeThreads).begin();
448
449 while (threads != (*activeThreads).end()) {
450 unsigned tid = *threads++;
451
452 if (decodeStatus[tid] == Unblocking) {
453 any_unblocking = true;
454 break;
455 }
456 }
457
458 // Decode will have activity if it's unblocking.
459 if (any_unblocking) {
460 if (_status == Inactive) {
461 _status = Active;
462
463 DPRINTF(Activity, "Activating stage.\n");
464
465 cpu->activateStage(O3CPU::DecodeIdx);
466 }
467 } else {
468 // If it's not unblocking, then decode will not have any internal
469 // activity. Switch it to inactive.
470 if (_status == Active) {
471 _status = Inactive;
472 DPRINTF(Activity, "Deactivating stage.\n");
473
474 cpu->deactivateStage(O3CPU::DecodeIdx);
475 }
476 }
477}
478
479template <class Impl>
480void
481DefaultDecode<Impl>::sortInsts()
482{
483 int insts_from_fetch = fromFetch->size;
484#ifdef DEBUG
485 for (int i=0; i < numThreads; i++)
486 assert(insts[i].empty());
487#endif
488 for (int i = 0; i < insts_from_fetch; ++i) {
489 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
490 }
491}
492
493template<class Impl>
494void
495DefaultDecode<Impl>::readStallSignals(unsigned tid)
496{
497 if (fromRename->renameBlock[tid]) {
498 stalls[tid].rename = true;
499 }
500
501 if (fromRename->renameUnblock[tid]) {
502 assert(stalls[tid].rename);
503 stalls[tid].rename = false;
504 }
505
506 if (fromIEW->iewBlock[tid]) {
507 stalls[tid].iew = true;
508 }
509
510 if (fromIEW->iewUnblock[tid]) {
511 assert(stalls[tid].iew);
512 stalls[tid].iew = false;
513 }
514
515 if (fromCommit->commitBlock[tid]) {
516 stalls[tid].commit = true;
517 }
518
519 if (fromCommit->commitUnblock[tid]) {
520 assert(stalls[tid].commit);
521 stalls[tid].commit = false;
522 }
523}
524
525template <class Impl>
526bool
527DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid)
528{
529 // Check if there's a squash signal, squash if there is.
530 // Check stall signals, block if necessary.
531 // If status was blocked
532 // Check if stall conditions have passed
533 // if so then go to unblocking
534 // If status was Squashing
535 // check if squashing is not high. Switch to running this cycle.
536
537 // Update the per thread stall statuses.
538 readStallSignals(tid);
539
540 // Check squash signals from commit.
541 if (fromCommit->commitInfo[tid].squash) {
542
543 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
544 "from commit.\n", tid);
545
546 squash(tid);
547
548 return true;
549 }
550
551 // Check ROB squash signals from commit.
552 if (fromCommit->commitInfo[tid].robSquashing) {
553 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
554
555 // Continue to squash.
556 decodeStatus[tid] = Squashing;
557
558 return true;
559 }
560
561 if (checkStall(tid)) {
562 return block(tid);
563 }
564
565 if (decodeStatus[tid] == Blocked) {
566 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
567 tid);
568
569 decodeStatus[tid] = Unblocking;
570
571 unblock(tid);
572
573 return true;
574 }
575
576 if (decodeStatus[tid] == Squashing) {
577 // Switch status to running if decode isn't being told to block or
578 // squash this cycle.
579 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
580 tid);
581
582 decodeStatus[tid] = Running;
583
584 return false;
585 }
586
587 // If we've reached this point, we have not gotten any signals that
588 // cause decode to change its status. Decode remains the same as before.
589 return false;
590}
591
592template<class Impl>
593void
594DefaultDecode<Impl>::tick()
595{
596 wroteToTimeBuffer = false;
597
598 bool status_change = false;
599
600 toRenameIndex = 0;
601
| 444
445 threads = (*activeThreads).begin();
446
447 while (threads != (*activeThreads).end()) {
448 unsigned tid = *threads++;
449
450 if (decodeStatus[tid] == Unblocking) {
451 any_unblocking = true;
452 break;
453 }
454 }
455
456 // Decode will have activity if it's unblocking.
457 if (any_unblocking) {
458 if (_status == Inactive) {
459 _status = Active;
460
461 DPRINTF(Activity, "Activating stage.\n");
462
463 cpu->activateStage(O3CPU::DecodeIdx);
464 }
465 } else {
466 // If it's not unblocking, then decode will not have any internal
467 // activity. Switch it to inactive.
468 if (_status == Active) {
469 _status = Inactive;
470 DPRINTF(Activity, "Deactivating stage.\n");
471
472 cpu->deactivateStage(O3CPU::DecodeIdx);
473 }
474 }
475}
476
477template <class Impl>
478void
479DefaultDecode<Impl>::sortInsts()
480{
481 int insts_from_fetch = fromFetch->size;
482#ifdef DEBUG
483 for (int i=0; i < numThreads; i++)
484 assert(insts[i].empty());
485#endif
486 for (int i = 0; i < insts_from_fetch; ++i) {
487 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
488 }
489}
490
491template<class Impl>
492void
493DefaultDecode<Impl>::readStallSignals(unsigned tid)
494{
495 if (fromRename->renameBlock[tid]) {
496 stalls[tid].rename = true;
497 }
498
499 if (fromRename->renameUnblock[tid]) {
500 assert(stalls[tid].rename);
501 stalls[tid].rename = false;
502 }
503
504 if (fromIEW->iewBlock[tid]) {
505 stalls[tid].iew = true;
506 }
507
508 if (fromIEW->iewUnblock[tid]) {
509 assert(stalls[tid].iew);
510 stalls[tid].iew = false;
511 }
512
513 if (fromCommit->commitBlock[tid]) {
514 stalls[tid].commit = true;
515 }
516
517 if (fromCommit->commitUnblock[tid]) {
518 assert(stalls[tid].commit);
519 stalls[tid].commit = false;
520 }
521}
522
523template <class Impl>
524bool
525DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid)
526{
527 // Check if there's a squash signal, squash if there is.
528 // Check stall signals, block if necessary.
529 // If status was blocked
530 // Check if stall conditions have passed
531 // if so then go to unblocking
532 // If status was Squashing
533 // check if squashing is not high. Switch to running this cycle.
534
535 // Update the per thread stall statuses.
536 readStallSignals(tid);
537
538 // Check squash signals from commit.
539 if (fromCommit->commitInfo[tid].squash) {
540
541 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
542 "from commit.\n", tid);
543
544 squash(tid);
545
546 return true;
547 }
548
549 // Check ROB squash signals from commit.
550 if (fromCommit->commitInfo[tid].robSquashing) {
551 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
552
553 // Continue to squash.
554 decodeStatus[tid] = Squashing;
555
556 return true;
557 }
558
559 if (checkStall(tid)) {
560 return block(tid);
561 }
562
563 if (decodeStatus[tid] == Blocked) {
564 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
565 tid);
566
567 decodeStatus[tid] = Unblocking;
568
569 unblock(tid);
570
571 return true;
572 }
573
574 if (decodeStatus[tid] == Squashing) {
575 // Switch status to running if decode isn't being told to block or
576 // squash this cycle.
577 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
578 tid);
579
580 decodeStatus[tid] = Running;
581
582 return false;
583 }
584
585 // If we've reached this point, we have not gotten any signals that
586 // cause decode to change its status. Decode remains the same as before.
587 return false;
588}
589
590template<class Impl>
591void
592DefaultDecode<Impl>::tick()
593{
594 wroteToTimeBuffer = false;
595
596 bool status_change = false;
597
598 toRenameIndex = 0;
599
|
602 list::iterator threads = (*activeThreads).begin();
| 600 std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
603
604 sortInsts();
605
606 //Check stall and squash signals.
607 while (threads != (*activeThreads).end()) {
608 unsigned tid = *threads++;
609
610 DPRINTF(Decode,"Processing [tid:%i]\n",tid);
611 status_change = checkSignalsAndUpdate(tid) || status_change;
612
613 decode(status_change, tid);
614 }
615
616 if (status_change) {
617 updateStatus();
618 }
619
620 if (wroteToTimeBuffer) {
621 DPRINTF(Activity, "Activity this cycle.\n");
622
623 cpu->activityThisCycle();
624 }
625}
626
627template<class Impl>
628void
629DefaultDecode<Impl>::decode(bool &status_change, unsigned tid)
630{
631 // If status is Running or idle,
632 // call decodeInsts()
633 // If status is Unblocking,
634 // buffer any instructions coming from fetch
635 // continue trying to empty skid buffer
636 // check if stall conditions have passed
637
638 if (decodeStatus[tid] == Blocked) {
639 ++decodeBlockedCycles;
640 } else if (decodeStatus[tid] == Squashing) {
641 ++decodeSquashCycles;
642 }
643
644 // Decode should try to decode as many instructions as its bandwidth
645 // will allow, as long as it is not currently blocked.
646 if (decodeStatus[tid] == Running ||
647 decodeStatus[tid] == Idle) {
648 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
649 "stage.\n",tid);
650
651 decodeInsts(tid);
652 } else if (decodeStatus[tid] == Unblocking) {
653 // Make sure that the skid buffer has something in it if the
654 // status is unblocking.
655 assert(!skidsEmpty());
656
657 // If the status was unblocking, then instructions from the skid
658 // buffer were used. Remove those instructions and handle
659 // the rest of unblocking.
660 decodeInsts(tid);
661
662 if (fetchInstsValid()) {
663 // Add the current inputs to the skid buffer so they can be
664 // reprocessed when this stage unblocks.
665 skidInsert(tid);
666 }
667
668 status_change = unblock(tid) || status_change;
669 }
670}
671
672template <class Impl>
673void
674DefaultDecode<Impl>::decodeInsts(unsigned tid)
675{
676 // Instructions can come either from the skid buffer or the list of
677 // instructions coming from fetch, depending on decode's status.
678 int insts_available = decodeStatus[tid] == Unblocking ?
679 skidBuffer[tid].size() : insts[tid].size();
680
681 if (insts_available == 0) {
682 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
683 " early.\n",tid);
684 // Should I change the status to idle?
685 ++decodeIdleCycles;
686 return;
687 } else if (decodeStatus[tid] == Unblocking) {
688 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
689 "buffer.\n",tid);
690 ++decodeUnblockCycles;
691 } else if (decodeStatus[tid] == Running) {
692 ++decodeRunCycles;
693 }
694
695 DynInstPtr inst;
696
697 std::queue<DynInstPtr>
698 &insts_to_decode = decodeStatus[tid] == Unblocking ?
699 skidBuffer[tid] : insts[tid];
700
701 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
702
703 while (insts_available > 0 && toRenameIndex < decodeWidth) {
704 assert(!insts_to_decode.empty());
705
706 inst = insts_to_decode.front();
707
708 insts_to_decode.pop();
709
710 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
711 "PC %#x\n",
712 tid, inst->seqNum, inst->readPC());
713
714 if (inst->isSquashed()) {
715 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is "
716 "squashed, skipping.\n",
717 tid, inst->seqNum, inst->readPC());
718
719 ++decodeSquashedInsts;
720
721 --insts_available;
722
723 continue;
724 }
725
726 // Also check if instructions have no source registers. Mark
727 // them as ready to issue at any time. Not sure if this check
728 // should exist here or at a later stage; however it doesn't matter
729 // too much for function correctness.
730 if (inst->numSrcRegs() == 0) {
731 inst->setCanIssue();
732 }
733
734 // This current instruction is valid, so add it into the decode
735 // queue. The next instruction may not be valid, so check to
736 // see if branches were predicted correctly.
737 toRename->insts[toRenameIndex] = inst;
738
739 ++(toRename->size);
740 ++toRenameIndex;
741 ++decodeDecodedInsts;
742 --insts_available;
743
744 // Ensure that if it was predicted as a branch, it really is a
745 // branch.
746 if (inst->predTaken() && !inst->isControl()) {
747 DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n",inst->predPC,
748 inst->nextPC + 4);
749
750 panic("Instruction predicted as a branch!");
751
752 ++decodeControlMispred;
753
754 // Might want to set some sort of boolean and just do
755 // a check at the end
756 squash(inst, inst->threadNumber);
757
758 break;
759 }
760
761 // Go ahead and compute any PC-relative branches.
762 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
763 ++decodeBranchResolved;
764
765 if (inst->branchTarget() != inst->readPredTarg()) {
766 ++decodeBranchMispred;
767
768 // Might want to set some sort of boolean and just do
769 // a check at the end
770#if THE_ISA == ALPHA_ISA
771 squash(inst, inst->threadNumber);
772 inst->setPredTarg(inst->branchTarget());
773 break;
774#else
775 // If mispredicted as taken, then ignore delay slot
776 // instruction... else keep delay slot and squash
777 // after it is sent to rename
778 if (inst->predTaken() && inst->isCondDelaySlot()) {
779 DPRINTF(Decode, "[tid:%i]: Conditional delay slot inst."
780 "[sn:%i] PC %#x mispredicted as taken.\n", tid,
781 inst->seqNum, inst->PC);
782 bdelayDoneSeqNum[tid] = inst->seqNum;
783 squash(inst, inst->threadNumber);
784 inst->setPredTarg(inst->branchTarget());
785 break;
786 } else {
787 DPRINTF(Decode, "[tid:%i]: Misprediction detected at "
788 "[sn:%i] PC %#x, will squash after delay slot "
789 "inst. is sent to Rename\n",
790 tid, inst->seqNum, inst->PC);
791 bdelayDoneSeqNum[tid] = inst->seqNum + 1;
792 squashAfterDelaySlot[tid] = true;
793 squashInst[tid] = inst;
794 continue;
795 }
796#endif
797 }
798 }
799
800 if (squashAfterDelaySlot[tid]) {
801 assert(!inst->isSquashed());
802 squash(squashInst[tid], squashInst[tid]->threadNumber);
803 squashInst[tid]->setPredTarg(squashInst[tid]->branchTarget());
804 assert(!inst->isSquashed());
805 break;
806 }
807 }
808
809 // If we didn't process all instructions, then we will need to block
810 // and put all those instructions into the skid buffer.
811 if (!insts_to_decode.empty()) {
812 block(tid);
813 }
814
815 // Record that decode has written to the time buffer for activity
816 // tracking.
817 if (toRenameIndex) {
818 wroteToTimeBuffer = true;
819 }
820}
| 601
602 sortInsts();
603
604 //Check stall and squash signals.
605 while (threads != (*activeThreads).end()) {
606 unsigned tid = *threads++;
607
608 DPRINTF(Decode,"Processing [tid:%i]\n",tid);
609 status_change = checkSignalsAndUpdate(tid) || status_change;
610
611 decode(status_change, tid);
612 }
613
614 if (status_change) {
615 updateStatus();
616 }
617
618 if (wroteToTimeBuffer) {
619 DPRINTF(Activity, "Activity this cycle.\n");
620
621 cpu->activityThisCycle();
622 }
623}
624
625template<class Impl>
626void
627DefaultDecode<Impl>::decode(bool &status_change, unsigned tid)
628{
629 // If status is Running or idle,
630 // call decodeInsts()
631 // If status is Unblocking,
632 // buffer any instructions coming from fetch
633 // continue trying to empty skid buffer
634 // check if stall conditions have passed
635
636 if (decodeStatus[tid] == Blocked) {
637 ++decodeBlockedCycles;
638 } else if (decodeStatus[tid] == Squashing) {
639 ++decodeSquashCycles;
640 }
641
642 // Decode should try to decode as many instructions as its bandwidth
643 // will allow, as long as it is not currently blocked.
644 if (decodeStatus[tid] == Running ||
645 decodeStatus[tid] == Idle) {
646 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
647 "stage.\n",tid);
648
649 decodeInsts(tid);
650 } else if (decodeStatus[tid] == Unblocking) {
651 // Make sure that the skid buffer has something in it if the
652 // status is unblocking.
653 assert(!skidsEmpty());
654
655 // If the status was unblocking, then instructions from the skid
656 // buffer were used. Remove those instructions and handle
657 // the rest of unblocking.
658 decodeInsts(tid);
659
660 if (fetchInstsValid()) {
661 // Add the current inputs to the skid buffer so they can be
662 // reprocessed when this stage unblocks.
663 skidInsert(tid);
664 }
665
666 status_change = unblock(tid) || status_change;
667 }
668}
669
670template <class Impl>
671void
672DefaultDecode<Impl>::decodeInsts(unsigned tid)
673{
674 // Instructions can come either from the skid buffer or the list of
675 // instructions coming from fetch, depending on decode's status.
676 int insts_available = decodeStatus[tid] == Unblocking ?
677 skidBuffer[tid].size() : insts[tid].size();
678
679 if (insts_available == 0) {
680 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
681 " early.\n",tid);
682 // Should I change the status to idle?
683 ++decodeIdleCycles;
684 return;
685 } else if (decodeStatus[tid] == Unblocking) {
686 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
687 "buffer.\n",tid);
688 ++decodeUnblockCycles;
689 } else if (decodeStatus[tid] == Running) {
690 ++decodeRunCycles;
691 }
692
693 DynInstPtr inst;
694
695 std::queue<DynInstPtr>
696 &insts_to_decode = decodeStatus[tid] == Unblocking ?
697 skidBuffer[tid] : insts[tid];
698
699 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
700
701 while (insts_available > 0 && toRenameIndex < decodeWidth) {
702 assert(!insts_to_decode.empty());
703
704 inst = insts_to_decode.front();
705
706 insts_to_decode.pop();
707
708 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
709 "PC %#x\n",
710 tid, inst->seqNum, inst->readPC());
711
712 if (inst->isSquashed()) {
713 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is "
714 "squashed, skipping.\n",
715 tid, inst->seqNum, inst->readPC());
716
717 ++decodeSquashedInsts;
718
719 --insts_available;
720
721 continue;
722 }
723
724 // Also check if instructions have no source registers. Mark
725 // them as ready to issue at any time. Not sure if this check
726 // should exist here or at a later stage; however it doesn't matter
727 // too much for function correctness.
728 if (inst->numSrcRegs() == 0) {
729 inst->setCanIssue();
730 }
731
732 // This current instruction is valid, so add it into the decode
733 // queue. The next instruction may not be valid, so check to
734 // see if branches were predicted correctly.
735 toRename->insts[toRenameIndex] = inst;
736
737 ++(toRename->size);
738 ++toRenameIndex;
739 ++decodeDecodedInsts;
740 --insts_available;
741
742 // Ensure that if it was predicted as a branch, it really is a
743 // branch.
744 if (inst->predTaken() && !inst->isControl()) {
745 DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n",inst->predPC,
746 inst->nextPC + 4);
747
748 panic("Instruction predicted as a branch!");
749
750 ++decodeControlMispred;
751
752 // Might want to set some sort of boolean and just do
753 // a check at the end
754 squash(inst, inst->threadNumber);
755
756 break;
757 }
758
759 // Go ahead and compute any PC-relative branches.
760 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
761 ++decodeBranchResolved;
762
763 if (inst->branchTarget() != inst->readPredTarg()) {
764 ++decodeBranchMispred;
765
766 // Might want to set some sort of boolean and just do
767 // a check at the end
768#if THE_ISA == ALPHA_ISA
769 squash(inst, inst->threadNumber);
770 inst->setPredTarg(inst->branchTarget());
771 break;
772#else
773 // If mispredicted as taken, then ignore delay slot
774 // instruction... else keep delay slot and squash
775 // after it is sent to rename
776 if (inst->predTaken() && inst->isCondDelaySlot()) {
777 DPRINTF(Decode, "[tid:%i]: Conditional delay slot inst."
778 "[sn:%i] PC %#x mispredicted as taken.\n", tid,
779 inst->seqNum, inst->PC);
780 bdelayDoneSeqNum[tid] = inst->seqNum;
781 squash(inst, inst->threadNumber);
782 inst->setPredTarg(inst->branchTarget());
783 break;
784 } else {
785 DPRINTF(Decode, "[tid:%i]: Misprediction detected at "
786 "[sn:%i] PC %#x, will squash after delay slot "
787 "inst. is sent to Rename\n",
788 tid, inst->seqNum, inst->PC);
789 bdelayDoneSeqNum[tid] = inst->seqNum + 1;
790 squashAfterDelaySlot[tid] = true;
791 squashInst[tid] = inst;
792 continue;
793 }
794#endif
795 }
796 }
797
798 if (squashAfterDelaySlot[tid]) {
799 assert(!inst->isSquashed());
800 squash(squashInst[tid], squashInst[tid]->threadNumber);
801 squashInst[tid]->setPredTarg(squashInst[tid]->branchTarget());
802 assert(!inst->isSquashed());
803 break;
804 }
805 }
806
807 // If we didn't process all instructions, then we will need to block
808 // and put all those instructions into the skid buffer.
809 if (!insts_to_decode.empty()) {
810 block(tid);
811 }
812
813 // Record that decode has written to the time buffer for activity
814 // tracking.
815 if (toRenameIndex) {
816 wroteToTimeBuffer = true;
817 }
818}
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